800 mA, DC-to-DC Inverting Regulator Data Sheet ADP5075 FEATURES TYPICAL APPLICATION CIRCUIT Wide input voltage range: 2.85 V to 15 V C VREF Adjustable negative output to V 39 V AVIN VREF IN V Integrated 800 mA main switch IN PVIN R FB C 1.2 MHz/2.4 MHz switching frequency with optional external IN ADP5075 FB frequency synchronization from 1.0 MHz to 2.6 MHz R FT ON Resistor programmable soft start timer OFF EN D1 Slew rate control for lower system noise SW V OUT SS Precision enable control C OUT R L1 C UVLO, OCP, OVP, and TSD protection COMP SLEW C C 1.61 mm 2.18 mm, 12-ball WLCSP SYNC/FREQ VREG 40C to +125C junction temperature range C VREG GND Supported by the ADIsimPower tool set APPLICATIONS Figure 1. Bipolar amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and multiplexers Charge coupled device (CCD) bias supplies Optical module supplies Radio frequency (RF) power amplifier (PA) bias GENERAL DESCRIPTION The ADP5075 is a high performance dc-to-dc inverting regulator Other key safety features in the ADP5075 include overcurrent used to generate negative supply rails. protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch enables the generation of The ADP5075 is available in a 12-ball WLCSP and is rated for a an adjustable negative output voltage down to 39 V below the input 40C to +125C junction temperature range. voltage. Table 1. Related Devices The ADP5075 operates at a pin selected 1.2 MHz/2.4 MHz Boost Inverter switching frequency. The ADP5075 can synchronize with an Device Switch (A) Switch (A) Package external oscillator from 1.0 MHz to 2.6 MHz to ease noise ADP5070 1.0 0.6 20-lead LFCSP (4 mm 4 mm) and 20-lead TSSOP filtering in sensitive applications. The regulator implements ADP5071 2.0 1.2 20-lead LFCSP (4 mm programmable slew rate control circuitry for the MOSFET 4 mm) and 20-lead TSSOP driver stage to reduce electromagnetic interference (EMI). ADP5075 Not 0.8 12-ball WLCSP The ADP5075 includes a fixed internal or resistor programmable applicable (1.61 mm 2.18 mm) soft start timer to prevent inrush current at power-up. During shutdown, the regulator completely disconnects the load from the input supply to provide a true shutdown. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20152017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 12819-001ADP5075 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Regulators ..................................................................... 11 Applications ....................................................................................... 1 Precision Enabling...................................................................... 11 Typical Application Circuit ............................................................. 1 Soft Start ...................................................................................... 12 General Description ......................................................................... 1 Slew Rate Control ....................................................................... 12 Revision History ............................................................................... 2 Current-Limit Protection ............................................................ 12 Specifications ..................................................................................... 3 Overvoltage Protection .............................................................. 12 Absolute Maximum Ratings ............................................................ 5 Thermal Shutdown .................................................................... 12 Thermal Resistance ...................................................................... 5 Applications Information .............................................................. 13 ESD Caution .................................................................................. 5 ADIsimPower Design Tool ....................................................... 13 Pin Configuration and Function Descriptions ............................. 6 Component Selection ................................................................ 13 Typical Performance Characteristics ............................................. 7 Common Applications .............................................................. 16 Theory of Operation ...................................................................... 11 Layout Considerations ............................................................... 18 PWM Mode ................................................................................. 11 Outline Dimensions ....................................................................... 19 PSM Mode ................................................................................... 11 Ordering Guide .......................................................................... 19 Undervoltage Lockout (UVLO) ............................................... 11 Oscillator and Synchronization ................................................ 11 REVISION HISTORY 9/2017Rev. A to Rev. B Changes to Table 9 .......................................................................... 17 8/2015Rev. 0 to Rev. A Changes to General Description Section and Figure 1 ............... 1 Change to Figure 23 ....................................................................... 11 7/2015Revision 0: Initial Version Rev. B Page 2 of 19