Keypad Decoder and I/O Expansion Data Sheet ADP5585 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND 16-element FIFO for event recording 10 configurable I/Os allowing functions such as ADP5585 Key pad decoding for a matrix of up to 5 5 UVLO RST/R5 OSCILLATOR POR 11 GPIOs (5 6) with ADP5585ACxZ-01-R7 models SDA 2 I C INTERFACE Key press/release interrupts SCL GPIO functions INT GPI with selectable interrupt level KEY SCAN 100 k or 300 k pull-up resistors R0 AND DECODE 300 k pull-down resistors R1 GPO with push-pull or open-drain GPI SCAN R2 REGISTERS AND Programmable logic block R3 DECODE R4 I/O PWM generator CONFIG LOGIC C0 Internal PWM generation C1 PWM External PWM with internal PWM AND function C2 Reset generators RESET1 C3 2 GEN I C interface with fast mode plus (Fm+) support of up to 1 MHz C4 RESET2 Open-drain interrupt output GEN 16-ball WLCSP, 1.59 mm 1.59 mm Figure 1. 16-lead LFCSP, 3 mm 3 mm APPLICATIONS Keypad entries and input/output expansion capabilities Smart phones, remote controls, and cameras Healthcare, industrial, and instrumentation GENERAL DESCRIPTION The ADP5585 is a 10 input/output port expander with a built in as events via the FIFO, eliminating the need to monitor different keypad matrix decoder, programmable logic, reset generator, and registers for event changes. The ADP5585 is equipped with a PWM generator. Input/output expander ICs are used in portable FIFO to store up to 16 events. Events can be read back by the 2 devices (phones, remote controls, and cameras) and nonportable processor via an I C-compatible interface. applications (healthcare, industrial, and instrumentation). I/O The ADP5585 frees up the main processor from having to expanders can be used to increase the number of I/Os available monitor the keypad, thereby reducing power consumption to a processor or to reduce the number of I/Os required through and/or increasing processor bandwidth for performing other interface connectors for front panel designs. functions. The ADP5585 handles all key scanning and decoding and can The programmable logic functions allow common logic require- flag the main processor via an interrupt line that new key events ments to be integrated as part of the GPIO expander, thus saving have occurred. GPI changes and logic changes can also be tracked board area and cost. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09841-001ADP5585 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Functional Description .....................................................................9 Applications ....................................................................................... 1 Event FIFO .....................................................................................9 Functional Block Diagram .............................................................. 1 Key Scan Control ...........................................................................9 General Description ......................................................................... 1 GPI Input ..................................................................................... 12 Revision History ............................................................................... 2 GPO Output ................................................................................ 12 Specifications ..................................................................................... 3 Logic Blocks ................................................................................ 12 Timing Diagram ........................................................................... 4 PWM Block ................................................................................. 13 Absolute Maximum Ratings ............................................................ 5 Reset Blocks ................................................................................ 14 Thermal Resistance ...................................................................... 5 Register Interface ............................................................................ 15 ESD Caution .................................................................................. 5 Register Map ................................................................................... 17 Pin Configurations and Function Descriptions ........................... 6 Detailed Register Descriptions ................................................. 19 Theory of Operation ........................................................................ 7 Applications Diagram .................................................................... 36 Device Enable ................................................................................ 8 Outline Dimensions ....................................................................... 37 Device Overview .......................................................................... 8 Ordering Guide .......................................................................... 38 REVISION HISTORY 1/13Rev. B to Rev. C 10/11Rev. Sp0 to Rev. A Changes to Detailed Register Description Section .................... 19 Added 16-Lead LFCSP WQ Package .............................. Universal Changes to Table 31 and Table 32 ................................................ 24 Changes to Features Section ............................................................ 1 Changes to Table 33, Table 34, and Table 35 ............................... 25 Added Figure 4 Renumbered Sequentially ................................... 6 Changes to Table 37 ........................................................................ 26 Changes to Table 4 ............................................................................. 6 Changes to Table 39 ........................................................................ 27 Changes to Device Enable Section and Table 5 ............................. 8 Changes to Table 41 and Table 43 ................................................ 28 Change to General Section ............................................................ 11 Changes to Table 45 ........................................................................ 29 Changes to Logic Blocks Section .................................................. 12 Changes to Table 47 ........................................................................ 30 Changes to PWM Block Section .................................................. 13 Changes to Table 64 ........................................................................ 34 Changes to Interrupts Section ...................................................... 14 Changes to Figure 27 ...................................................................... 36 Changes to Register Interface Section ......................................... 15 Changes to Figure 27 ...................................................................... 35 7/12Rev. A to Rev B Updated Outline Dimensions ....................................................... 36 Changes to Table 5 ............................................................................ 8 Changes to Ordering Guide .......................................................... 38 Updated Outline Dimensions ....................................................... 36 Changes to Ordering Guide .......................................................... 37 5/11Revision Sp0: Initial Version Rev. C Page 2 of 40