Keypad Decoder and I/O Expansion Data Sheet ADP5589 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD GND 16-element FIFO for event recording 19 configurable I/Os allowing functions such as ADP5589 Keypad decoding for matrix up to 11 8 UVLO RST OSCILLATOR POR Key press/release interrupts SDA 2 Key pad lock/unlock I C INTERFACE SCL GPIO functions INT GPI with selectable interrupt level R0 100 k or 300 k pull-up resistors R1 300 k pull-down resistors KEY SCAN R2 AND GPO with push-pull or open drain DECODE R3 Dual programmable logic blocks R4 PWM generator R5 GPI SCAN Internal PWM generation R6 AND DECODE External PWM with internal PWM AND function R7 REGISTERS Clock divider C0 I/O LOGIC 1 CONFIG Reset generators C1 2 C2 I C interface with fast-mode plus (Fm+) support up to 1 MHz LOGIC 2 C3 Open-drain interrupt output C4 24-lead LFCSP 3.5 mm 3.5 mm CLK DIV C5 25-ball WLCSP 1.99 mm 1.99 mm C6 PWM C7 RESET 1 APPLICATIONS C8 GEN C9 Devices requiring keypad entry and I/O expansion RESET 2 C10 GEN capabilities Figure 1. GENERAL DESCRIPTION The ADP5589 is a 19 I/O port expander with built-in keypad need to monitor different registers for event changes. The matrix decoder, programmable logic, reset generator, and ADP5589 is equipped with a FIFO to store up to 16 events. 2 PWM generator. I/O expander ICs are used in portable devices Events can be read back by the processor via an I C compatible (phones, remote controls, and cameras) and nonportable interface. applications (healthcare, industrial, and instrumentation). I/O The ADP5589 frees up the main processor from having to expanders can be used to increase the number of I/Os available monitor the keypad, thereby reducing power consumption to a processor or to reduce the number of I/Os required and/or increasing processor bandwidth for performing other through interface connectors for front panel designs. functions. The ADP5589, which handles all key scanning and decoding, The programmable logic functions allow common logic can flag the main processor via an interrupt line when new key requirements to be integrated as part of the GPIO expander, events have occurred. In addition, GPI changes and logic saving board area and cost. changes can be tracked as events via the FIFO, eliminating the Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20112013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 09714-001ADP5589 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Event FIFO .....................................................................................9 Applications ....................................................................................... 1 Key Scan Control ...........................................................................9 Functional Block Diagram .............................................................. 1 GPO Output ................................................................................ 15 General Description ......................................................................... 1 Logic Blocks ................................................................................ 16 Revision History ............................................................................... 2 PWM Block ................................................................................. 17 Specifications ..................................................................................... 3 Clock Divider Block ................................................................... 17 Absolute Maximum Ratings ............................................................ 5 Reset Blocks ................................................................................ 17 Thermal Resistance ...................................................................... 5 Interrupts ..................................................................................... 18 ESD Caution .................................................................................. 5 Register Interface ............................................................................ 19 Pin Configuration and Function Descriptions ............................. 6 Register Map ................................................................................... 21 Quick Device Overview ................................................................... 7 Detailed Register Descriptions ................................................. 23 Device Enable ................................................................................ 8 Application Diagram ...................................................................... 48 Device Overview .......................................................................... 8 Outline Dimensions ....................................................................... 49 Detailed Description ........................................................................ 9 Ordering Guide .......................................................................... 49 REVISION HISTORY 1/13Rev. A to Rev. B Changes to Detailed Register Descriptions Section and Table 7 .............................................................................................. 22 Changes to Table 33 and Table 34 ................................................ 29 Changes to Table 36 ........................................................................ 30 Changes to Table 37 ........................................................................ 31 Changes to Table 69 ........................................................................ 41 Changes to Table 84 ........................................................................ 46 Changes to Figure 31 ...................................................................... 48 8/11Revision A: Initial Version Rev. B Page 2 of 52