20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator Data Sheet ADP7112 FEATURES TYPICAL APPLICATION CIRCUITS Low noise: 11 V rms independent of fixed output voltage ADP7112 V = 6V V = 5V PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, IN OUT VIN VOUT V = 5 V, V = 7 V C C OUT IN IN OUT 2.2F 2.2F Input voltage range: 2.7 V to 20 V SENSE/ADJ ON Maximum output current: 200 mA EN SS Initial accuracy: 0.8% C GND SS OFF 1nF Accuracy over line, load, and temperature 1.8%, T = 40C to +125C J Figure 1. ADP7112 with Fixed Output Voltage, 5 V Low dropout voltage: 200 mV (typical) at a 200 mA load, V = 5 V OUT ADP7112 User-programmable soft start V = 7V V = 6V IN OUT VIN VOUT Low quiescent current, I = 50 A (typical) with no load GND C C IN 2k OUT 2.2F 2.2F SENSE/ADJ Low shutdown current 10k 1.8 A at V = 5 V ON IN EN SS 3.0 A at V = 20 V IN C GND SS OFF 1nF Stable with a small 2.2 F ceramic output capacitor Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V Figure 2. ADP7112 with 5 V Output Adjusted to 6 V 15 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to V V , output can be IN DO adjusted above initial set point Precision enable 1 mm 1.2 mm, 6-ball WLCSP APPLICATIONS Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7112 is a CMOS, low dropout (LDO) linear regulator The ADP7112 is available in 15 fixed output voltage options. that operates from 2.7 V to 20 V and provides up to 200 mA of The following voltages are available from stock: 1.2 V output current. This high input voltage LDO is ideal for the (adjustable), 1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages regulation of high performance analog and mixed-signal circuits available by special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, operating from 19 V down to 1.2 V rails. Using an advanced 2.8 V, 2.85 V, 3.8 V, 4.2 V, and 4.6 V. proprietary architecture, the device provides high power supply Each fixed output voltage can be adjusted above the initial set rejection, low noise, and achieves excellent line and load transient point with an external feedback divider. This allows the ADP7112 response with a small 2.2 F ceramic output capacitor. The to provide an output voltage from 1.2 V to V V with high IN DO ADP7112 regulator output noise is 11 V rms, independent of PSRR and low noise. the output voltage for the fixed options of 5 V or less. A user-programmable soft start with an external capacitor is available in the ADP7112. The ADP7112 is available in a 6-ball 1 mm 1.2 mm WLCSP, making it a very compact solution. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20142020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. 12508-001 12508-002ADP7112 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ...................................................................................... 1 Applications Information ............................................................. 14 Typical Application Circuits ........................................................... 1 Capacitor Selection .................................................................... 14 General Description ......................................................................... 1 Programable Precision Enable ................................................. 15 Revision History ............................................................................... 2 Soft Start ...................................................................................... 15 Specifications .................................................................................... 3 Noise Reduction of the ADP7112 in Adjustable Mode ........ 16 Input and Output Capacitance, Recommended Specifications Current-Limit and Thermal Overload Protection ................ 16 ......................................................................................................... 4 Effect of Noise Reduction on Start-Up Time ......................... 16 Absolute Maximum Ratings ........................................................... 5 Thermal Considerations ........................................................... 17 Thermal Data ................................................................................ 5 PCB Layout Considerations .......................................................... 19 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 21 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 21 Pin Configuration and Function Descriptions ............................ 6 Typical Performance Characteristics ............................................. 7 REVISION HISTORY 3/2020Rev. C to Rev. D 12/2014Rev. A to Rev. B Change to General Description Section ........................................ 1 Changed EN to GND Parameter from 0.3 V to VIN to 0.3 V Changes to Shutdown Current Parameter, Table 1 ..................... 3 to +24 V, Table 3 ............................................................................... 5 Changes to Theory of Operation Section .................................... 13 Change to Effect of Noise Reduction on Start-Up Time Section ... 16 12/2014Rev. 0 to Rev. A Changes to Table 7 ......................................................................... 20 Changes to Figure 34 to Figure 39 ............................................... 12 Changes to Figure 42 ..................................................................... 14 7/2016Rev. B to Rev. C Changes to Figure 40 ..................................................................... 13 9/2014Revision 0: Initial Version Changes to Programmable Precision Enable Section and Soft Start Section ..................................................................................... 15 Added Effect of Noise Reduction on Start-Up Time Section .. 16 Rev. D Page 2 of 21