1.2 A, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADP7157 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V ADP7157 Adjustable output voltage range (VOUT): 1.2 V to 3.3 V V = 3.8V IN V = 3.3V OUT VIN VOUT Maximum load current: 1.2 A C C IN OUT 10F 10F VOUT SENSE Low noise ON 0.9 V rms typical output noise from 100 Hz to 100 kHz EN REF C REF OFF 1F 1.6 V rms typical output noise from 10 Hz to 100 kHz R1 BYP Noise spectral density: 1.7 nV/Hz from 10 kHz to 1 MHz C BYP V = 1.2V (R1 + R2)/R2 OUT 1F REF SENSE Power supply rejection ratio (PSRR) R2 82 dB from 1 kHz to 100 kHz VREG C REG 1k < R2 < 200k 1F 55 dB at 1 MHz GND Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V Initial accuracy: 0.6% at ILOAD = 10 mA Figure 1. Regulated 3.3 V Output from a 3.8 V Input Accuracy over line, load, and temperature: 1.5% Operating supply current (IGND) 4.0 mA typical at 0 A 7.0 mA typical at 1.2 A Low shutdown current: 0.2 A typical Stable with a 10 F ceramic output capacitor 10-lead, 3 mm 3 mm LFCSP and 8-lead SOIC packages Table 1. Related Devices Precision enable Input Output Fixed/ Supported by ADIsimPower tool Model Voltage Current Adjustable Package APPLICATIONS ADP7159, 2.3 V to 2 A Fixed 10-lead LFCSP/ Regulation to noise sensitive applications: phase-locked ADP7158 5.5 V 8-lead SOIC loops (PLLs), voltage controlled oscillators (VCOs), and ADP7156 2.3 V to 1.2 A Fixed/ 10-lead LFCSP/ 5.5 V Adjustable 8-lead SOIC PLLs with integrated VCOs ADM7150, 4.5 V to 800 mA Fixed/ 8-lead LFCSP/ Communications and infrastructure ADM7151 16 V Adjustable 8-lead SOIC Backhaul and microwave links ADM7154, 2.3 V to 600 mA Fixed/ 8-lead LFCSP/ ADM7155 5.5 V Adjustable 8-lead SOIC GENERAL DESCRIPTION ADM7160 2.2 V to 200 mA Fixed 6-lead LFCSP/ The ADP7157 is an adjustable linear regulator that operates 5.5 V 5-lead TSOT from 2.3 V to 5.5 V and provides up to 1.2 A of output current. 1k C = 1F BYP Output voltages from 1.2 V to 3.3 V are possible depending on C = 10F BYP C = 100F BYP the model. Using an advanced proprietary architecture, the C = 1000F BYP device provides high power supply rejection and ultralow noise, 100 achieving excellent line and load transient response with only a 10 F ceramic output capacitor. 10 The ADP7157 is available in four models that optimize power dissipation and PSRR performance as a function of the input and output voltage. See Table 9 and Table 10 for selection guides. 1 The typical output noise the ADP7157 regulator is 0.9 V rms from 100 Hz to 100 kHz and 1.7 nV/Hz for noise spectral density from 10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm 0.1 3 mm LFCSP and 8-lead SOIC packages, making it not only a 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) very compact solution, but also providing excellent thermal performance for applications requiring up to 1.2 A of output Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V current in a small, low profile footprint. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com NOISE SPECTRAL DENSITY (nV/Hz) 12939-002 12938-001ADP7157 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADIsimPower Design Tool ....................................................... 14 Applications ....................................................................................... 1 Capacitor Selection .................................................................... 14 General Description ......................................................................... 1 Undervoltage Lockout (UVLO) ............................................... 15 Typical Application Circuit ............................................................. 1 Programmable Precision Enable .............................................. 16 Revision History ............................................................................... 2 Start-Up Time ............................................................................. 17 Specifications ..................................................................................... 3 REF, BYP, and VREG Pins......................................................... 17 Absolute Maximum Ratings ............................................................ 5 Current-Limit and Thermal Shutdown ................................... 17 Thermal Data ................................................................................ 5 Thermal Considerations ............................................................ 17 Thermal Resistance ...................................................................... 5 PSRR Performance ..................................................................... 20 ESD Caution .................................................................................. 5 PCB Layout Considerations .......................................................... 21 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 22 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 23 Theory of Operation ...................................................................... 13 Applications Information .............................................................. 14 REVISION HISTORY 11/2016Rev. A to Rev. B Changes to Table 3 ............................................................................ 4 5/2016Rev. 0 to Rev. A Added Note 2 to Table 2 Renumbered Sequentially ................... 4 Change to Figure 4 ........................................................................... 6 Change to Programmable Precision Enable Section ................. 16 3/2016Revision 0: Initial Version Rev. B Page 2 of 23