300 mA, Ultralow Noise, High PSRR, Low Dropout Linear Regulator Data Sheet ADP7183 FEATURES TYPICAL APPLICATION CIRCUITS Input voltage range: 2.0 V to 5.5 V EP Maximum output current: 300 mA V = 3.8V VIN VOUT V = 3.3V IN OUT C C Fixed output voltage options: 0.5 V to 4.5 V IN OUT 4.7F 4.7F SENSE Adjustable output from 0.5 V to V + 0.5 V IN ADP7183 +1.25V Low output noise: 4 V rms from 100 Hz to 100 kHz VA C C OFF 0V EN A AFB Noise spectral density: 20 nV/Hz, 10 kHz to 1 MHz 1F 10nF 1.3V VAFB ON Power supply rejection ratio (PSRR) at 300 mA load VREG GND 75 dB typical at 10 kHz C REG 62 dB typical at 100 kHz 1F 40 dB typical at 1 MHz Figure 1. ADP7183 with Fixed Output Voltage, VOUT = 3.3 V Low dropout voltage: 130 mV typical at I = 300 mA OUT Initial output voltage accuracy (V ): 0.5% at I = 10 mA OUT OUT EP Output voltage accuracy over line, load, and temperature: 2.6% V = 3V VIN VOUT V = 2.5V IN OUT Operating supply current (I ): 0.6 mA typical at no load C GND C IN OUT 4.7F 4.7F SENSE Low shutdown current: 2 A typical at V = 5.5 V IN ADP7183 Stable with small 4.7 F ceramic input and output capacitor +1.25V VA R1 C C A OFF 0V EN AFB Positive or negative enable logic 100k 10nF 1F 1.3V VAFB Current-limit and thermal overload protection ON R2 VREG GND 24.9k 8-lead, 2 mm 2 mm LFCSP package C REG Supported by ADIsimPOWER voltage regulator design tool 1F APPLICATIONS Figure 2. ADP7183 with Adjustable Output Voltage, V = 2.5 V OUT Regulation to noise sensitive applications: analog-to-digital converters (ADCs), digital-to-analog converters (DACs), precision amplifiers Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7183 is a complementary metal oxide semiconductor Additional voltages available by special order are 0.8 V, 0.9 V, (CMOS), low dropout (LDO) linear regulator that operates 1.3 V, 2.8 V, 4.2 V, and 4.5 V. An adjustable version is also from 2.0 V to 5.5 V and provides up to 300 mA of output available that allows output voltages that range from 0.5 V to current. This LDO regulator is ideal for regulation of high VIN + 0.5 V with an external feedback divider. performance analog and mixed-signal circuits operating The enable logic feature is capable of interfacing with positive from 0.5 V down to 4.5 V. Using an advanced proprietary or negative logic levels for maximum flexibility. architecture, the ADP7183 provides high PSRR and low noise, The ADP7183 regulator output noise is 4 V rms independent and it achieves excellent line and load transient response with a of the output voltage. The ADP7183 is available in an 8-lead, small 4.7 F ceramic output capacitor. 2 mm 2 mm LFCSP, making it not only a very compact The ADP7183 is available in 15 fixed output voltage options. solution but also providing excellent thermal performance for The following voltages are available from stock: 0.5 V, 1.0 V, applications requiring up to 300 mA of output current in a 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.5 V, 3.0 V, and 3.3 V. small, low profile footprint. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20162017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12897-002 12897-001ADP7183 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 13 Applications ....................................................................................... 1 Adjustable Mode Operation ..................................................... 13 Typical Application Circuits ............................................................ 1 Enable Pin Operation ................................................................ 13 General Description ......................................................................... 1 Start-Up Time ............................................................................. 14 Revision History ............................................................................... 2 Applications Information .............................................................. 15 Specifications ..................................................................................... 3 ADIsimPower Design Tool ....................................................... 15 Input and Output Capacitor Recommended Specifications ... 4 Capacitor Selection .................................................................... 15 Absolute Maximum Ratings ............................................................ 5 Undervoltage Lockout (UVLO) ............................................... 16 Thermal Data ................................................................................ 5 Current-Limit and Thermal Overload Protection ................. 16 Thermal Resistance ...................................................................... 5 Thermal Considerations ............................................................ 17 ESD Caution .................................................................................. 5 PCB Layout Considerations ...................................................... 18 Pin Configuration and Function Descriptions ............................. 6 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 19 REVISION HISTORY 5/2017Rev. A to Rev. B Change to Low Noise Reference Voltage Parameter, Table 1 ...... 3 Changes to Figure 31 to Figure 33 ................................................ 11 Changes to Input and Output Capacitor Properties Section and Figure 49 .......................................................................................... 16 2/2017Rev. 0 to Rev. A Changes to Specifications Section .................................................. 3 Change to Output Accuracy Voltage Parameter, Table 1 ............ 3 Changes to Ordering Guide .......................................................... 19 10/2016Revision 0: Initial Version Rev. B Page 2 of 19