PPG Optical Sensor Module with Integrated Red/IR Emitters and AFE Data Sheet ADPD144RI FEATURES GENERAL DESCRIPTION 2.8 mm 5.0 mm module with integrated optical components The ADPD144RI is a highly integrated, photometric front end 660 nm LED, 880 nm IR LED, and photodiode optimized for photoplethysmography (PPG) detection of blood Fully integrated AFE, ADC, LED drivers, and timing core oxygenation (SpO2) by synchronous detection in red and infrared Custom optical package for use under a glass window wavelengths. Synchronous measurement allows rejection of both Programmable 2-channel, 8.5 mA to 370 mA LED drivers dc and ac ambient light interference with extremely low power Provision to use external LED emitters consumption. Low power The module combines highly efficient, light emitting diode Specifically designed for ultralow direct optical reflections (LED) emitters and a sensitive 4-channel, deep diffusion Independent AFE settings per channel photodiode (PD1 to PD4) with a custom application specific 2 I C data and control interface integrated circuit (ASIC) in a compact package that provides Burst accumulator enabling 20 bits per sample period optical isolation between the integrated LED emitters and the Sample to sample accumulator enabling up to 27 bits per detection photodiodes to improve through tissue, signal-to- data read noise ratio (SNR). 16-bit or 32-bit register or FIFO readout per channel The ASIC consists of a 4-channel analog front end (AFE) with APPLICATIONS two independently configurable datapaths with separate gain Optical heart rate monitoring and filter settings, a 14-bit analog-to-digital converter (ADC) Reflective SpO2 measurement with a burst accumulator, two flexible, independently configurable, LED drivers, and a digital control block. The digital control block provides AFE and LED timing, signal processing, and communication. Data output and functional configuration 2 occur over a 1.8 V I C interface. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 ADPD144RI ANALOG BLOCK PD3 PD1 CH1 AMBIENT AFE TIA LIGHT GAIN REJECTION PD4 PD2 V BIAS CH2 AMBIENT AFE TIA LIGHT GAIN REJECTION AGND V BIAS VREF CH3 AMBIENT 1F VLED TIME SLOT A AFE TIA LIGHT LEDs GAIN DATA REJECTION 880nm V BIAS 14-BIT ADC SDA CH4 TIME SLOT B AMBIENT AFE DATA SCL AFE CONFIGURATION, TIA LIGHT GAIN TIME SLOT A REJECTION INT 660nm AFE CONFIGURATION, V BIAS DGND TIME SLOT B AFE: SIGNAL CONDITIONING DIGITAL INTERFACE AND CONTROL LED2 DRIVER LEDX2 LED1 DRIVER LED2 LEVEL AND TIMING CONTROL LEDX1 LED1 LEVEL AND TIMING CONTROL LGND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14060-001ADPD144RI Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LED Driver Operation ............................................................... 13 2 Applications ....................................................................................... 1 I C Serial Interface .......................................................................... 15 General Description ......................................................................... 1 Applications Information .............................................................. 16 Functional Block Diagram .............................................................. 1 Typical Connection Diagram ................................................... 16 Revision History ............................................................................... 2 Land Pattern ................................................................................ 16 Specif icat ions ..................................................................................... 3 Recommended Start-Up Sequence .......................................... 16 2 I C Digital Input/Output Specifications .................................... 4 Reading Data ............................................................................... 17 2 I C Timing Specifications ............................................................ 5 Clocks and Timing Calibration ................................................ 18 Absolute Maximum Ratings ............................................................ 6 Determining CVLED ..................................................................... 19 Thermal Resistance ...................................................................... 6 Determining the Average LED Current .................................. 20 Recommended Soldering Profile ............................................... 6 Calculating the Total Power Consumption ............................ 20 ESD Caution .................................................................................. 6 Optimizing SNR per Watt ......................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Mechanical Considerations for Covering the ADPD144RI . 22 Typical Performance Characteristics ............................................. 8 Sample Setup File SpO2 ............................................................. 22 Theory of Operation ........................................................................ 9 Register Listing ............................................................................... 23 Introduction .................................................................................. 9 LED Control Registers ............................................................... 26 Optical Components .................................................................... 9 AFE Configuration Registers .................................................... 28 Sampling Operation ................................................................... 10 System Registers ......................................................................... 29 Pulse Timing ............................................................................... 10 ADC Registers ............................................................................ 32 Time Slot Switch ......................................................................... 11 Data Registers ............................................................................. 33 State Machine Operation ........................................................... 12 Outline Dimensions ....................................................................... 34 Sample Mode Operation and Data Flow ................................. 12 Ordering Guide .......................................................................... 34 Adjustable Sampling Frequency ............................................... 13 REVISION HISTORY 2/2019Revision A: Initial Version Rev. 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