Integrated Optical Module with Ambient Light Rejection and Two LEDs Data Sheet ADPD188GG FEATURES GENERAL DESCRIPTION 3.8 mm 5.0 mm 0.9 mm module with integrated optical The ADPD188GG is a complete photometric system designed to components measure optical signals from ambient light and from synchronous 2 green LEDs, 2 PDs with IR cut filter reflected light emitting diode (LED) pulses. Synchronous measure- 2 external sensor inputs ment offers best-in-class rejection of ambient light interference, 3, 370 mA LED drivers both dc and ac. The module integrates a highly efficient photo- 20-bit burst accumulator enabling 20 bits per sample period metric front end, two LEDs, and two photodiode (PD). All of On-board sample to sample accumulator enabling up to these items are housed in a custom package that prevents light 27 bits per data read from going directly from the LED to the photodiode without first Custom optical package made to work under a glass window entering the subject. Optimized SNR for signal limited cases 2 The front end of the application specific integrated circuit (ASIC) I C or SPI communications consists of a control block, a 14-bit analog-to-digital converter APPLICATIONS (ADC) with a 20-bit burst accumulator, and three flexible, Optical heart rate monitoring independently configurable LED drivers. The control circuitry Reflective PPG measurement includes flexible LED signaling and synchronous detection. CNIBP measurement The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. The data output and 2 functional configuration occur over a 1.8 V I C interface or a serial peripheral interface (SPI) port. FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 PDC ADPD188GG PD1 EXT IN1 CH1 BPF 1 INTEGRATOR TIA VREF VREF PD2 1F EXT IN2 CH2 BPF 1 INTEGRATOR TIA VREF PDC PDET1 PD3 CS CH3 BPF 1 INTEGRATOR SCLK TIME SLOT A TIA VREF DATA MOSI PDET2 MISO 14-BIT PD4 ADC BPF CH4 TIME SLOT B 1 INTEGRATOR SDA DATA VLED1 SCL TIA VREF GREEN GPIO0 DIGITAL GPIO1 INTERFACE AND LED1/DNC LED1 DRIVER CONTROL LED3 DRIVER LED3 LED2 DRIVER LED2 LGND AGND DGND NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs. Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. 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Trademarks and registered trademarks are the property of their respective owners. 16111-001ADPD188GG Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 22 Applications ...................................................................................... 1 Land Pattern ............................................................................... 22 General Description ......................................................................... 1 Recommended Start-Up Sequence .......................................... 23 Functional Block Diagram .............................................................. 1 Reading Data ............................................................................... 23 Revision History ............................................................................... 2 Clocks and Timing Calibration ................................................ 24 Specifications .................................................................................... 3 Optional Timing Signals Available on GPIO0 and GPIO1 . 25 Analog Specifications ................................................................... 5 LED Driver Pins and LED Supply Voltage ............................. 26 Digital Specifications ................................................................... 6 LED Driver Operation ............................................................... 26 Timing Specifications .................................................................. 7 Determining the Average Current ........................................... 27 Absolute Maximum Ratings ........................................................... 9 Determining CVLED ..................................................................... 27 Thermal Resistance ...................................................................... 9 Using External LEDs ................................................................. 28 Recommended Soldering Profile ............................................... 9 Calculating Current Consumption .......................................... 28 ESD Caution.................................................................................. 9 Mechanical Considerations for Covering the ADPD188GG ... 31 Pin Configuration and Function Descriptions .......................... 10 TIA ADC Mode .......................................................................... 31 Typical Performance Characteristics ........................................... 11 Pulse Connect Mode .................................................................. 33 Theory of Operation ...................................................................... 13 Synchronous ECG and PPG Measurement Using TIA ADC Mode ............................................................................................ 34 Introduction ................................................................................ 13 Float Mode .................................................................................. 35 Optical Components .................................................................. 13 Register Listing ............................................................................... 42 Dual Time Slot Operation ......................................................... 14 LED Control Registers ............................................................... 46 Time Slot Switch ......................................................................... 15 AFE Configuration Registers .................................................... 48 Adjustable Sampling Frequency............................................... 16 Float Mode Registers ................................................................. 52 External Synchronization for Sampling .................................. 16 System Registers ......................................................................... 55 State Machine Operation .......................................................... 16 ADC Registers ............................................................................ 59 Normal Mode Operation and Data Flow ................................ 17 Data Registers ............................................................................. 60 Communications Interface ........................................................... 19 2 Outline Dimensions ....................................................................... 61 I C Interface ................................................................................ 19 Ordering Guide .......................................................................... 61 SPI Port ........................................................................................ 20 Applications Information .............................................................. 22 REVISION HISTORY 4/2020Rev. A to Rev. B 10/2018Rev. 0 to Rev. A Change to Applications Section ..................................................... 1 Changes to Figure 24 and Figure 25 ............................................ 22 Changes to Table 4 and Figure 2 .................................................... 7 Changes to Calibrating the 32 kHz Clock Section..................... 25 Change to Reset Column, Table 26 .............................................. 42 Added Improving SNR Using Integrator Chopping Section and Added Endnote 1, Table 27 ........................................................... 46 Figure 32 Renumbered Sequentially ........................................... 29 Changes to Table 32 ....................................................................... 55 Added Table 18 Renumbered Sequentially ............................... 30 Changes to Table 26 ....................................................................... 42 Changes to Table 29 ....................................................................... 50 Changes to Table 30 ....................................................................... 51 Changes to Address 0x58 Description Column, Table 31 ........ 53 2/2018Revision 0: Initial Version Rev. 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