Multimodal Sensor Front End Data Sheet ADPD4000/ADPD4001 FEATURES GENERAL DESCRIPTION Multimodal analog front end The ADPD4000/ADPD4001 operate as a complete multimodal 8 input channels with multiple operation modes to sensor front end, stimulating up to eight LEDs and measuring accommodate the following measurements: PPG, ECG, the return signal on up to eight separate current inputs. Twelve EDA, impedance, and temperature time slots are available, enabling 12 separate measurements per Dual channel processing with simultaneous sampling sampling period. 12 programmable time slots for synchronized sensor 2 The data output and functional configuration utilize an I C measurements interface on the ADPD4001 or a serial port interface (SPI) on Flexible input multiplexing to support differential and the ADPD4000. The control circuitry includes flexible LED single-ended sensor measurements signaling and synchronous detection. The devices use a 1.8 V 8 LED drivers, 4 of which can be driven simultaneously analog core and 1.8 V/3.3 V compatible digital input/output (I/O). Flexible sampling rate from 0.004 Hz to 9 kHz using internal oscillators The analog front end (AFE) rejects signal offsets and corruption On-chip digital filtering from asynchronous modulated interference, typically from SNR of transmit and receive signal chain: 90 dB ambient light, eliminating the need for optical filters or externally Ambient light rejection: 60 dB up to 1 kHz controlled dc cancellation circuitry. Multiple operating modes 400 mA total LED drive current are provided, enabling the ADPD4000/ ADPD4001 to be a Total system power dissipation: 50 W (combined LED and sensor hub for synchronous measurements of photodiodes, AFE power), continuous PPG measurement at 75 dB SNR, biopotential electrodes, resistance, capacitance, and temperature 25 Hz ODR, 100 nA/mA CTR sensors. 2 SPI and I C communications supported The ADPD4000/ADPD4001 are available in a 3.11 mm 256-byte FIFO 2.14 mm, 0.4 mm pitch, 33-ball WLCSP and 35-ball WLCSP. APPLICATIONS Wearable health and fitness monitors: heart rate monitors (HRMs), heart rate variability (HRV), stress, blood pressure estimation, SpO2, hydration, body composition Industrial monitoring: CO, CO2, smoke, and aerosol detection Home patient monitoring FUNCTIONAL BLOCK DIAGRAM AVDD DVDD1 LED4B ADPD4000/ADPD4001 DVDD2 LED3B IOVDD LED LEVEL LED2B AND LED1B AGND LED MUX CONTROL LED4A DRIVERS DGND LED3A IOGND LED2A HIGH FREQUENCY LED1A CS AND LOW SCLK FREQUENCY MOSI OSCILLATORS LGND DIGITAL PROCESSING, MISO INTEGRATOR INTERFACE AND TIMING TIMING CONTROL, SCL FIFO, PROGRAM AND SDA IN1 CH 1 SIGNAL IN2 DATA REGISTERS, CONDITIONING COMMUNICATIONS GPIO0 IN3 ADC IN4 GPIO1 TIA VREF GPIO2 IN5 IN6 GPIO3 CH 2 SIGNAL IN7 CONDITIONING IN8 VREF INTEGRATOR TIMING VC1 VC1 VOLTAGE VREF VC2 VC2 REFERENCES TIA VREF NOTES V ICM 1. CS, SCLK, MOSI, AND MISO PINS ARE ON THE ADPD4000. 2. SCL AND SDA PINS ARE ON THE ADPD4001. 3. TIA VREF IS THE INTERNAL VOLTAGE REFERENCE SIGNAL FOR THE TRANSIMPEDANCE AMPLIFIER. Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2019 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 17335-001ADPD4000/ADPD4001 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Time Slot Operation .................................................................. 20 Applications ....................................................................................... 1 Execution Modes ........................................................................ 21 General Description ......................................................................... 1 Host Interface .............................................................................. 22 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 25 Revision History ............................................................................... 2 Operating Mode Overview ....................................................... 25 Specifications ..................................................................................... 3 Single Integration Mode ............................................................ 25 Temperature and Power Specifications ..................................... 3 Multiple Integration Mode ........................................................ 33 Performance Specifications ......................................................... 3 Digital Integration Mode ........................................................... 34 Digital Specifications ................................................................... 5 TIA ADC Mode .......................................................................... 36 Timing Specifications .................................................................. 6 Register Map ................................................................................... 38 Absolute Maximum Ratings ............................................................ 8 Register Details ............................................................................... 57 Thermal Resistance ...................................................................... 8 Global Configuration Registers ................................................ 57 Recommended Soldering Profile ............................................... 8 Interrupt Status and Control Registers .................................... 59 ESD Caution .................................................................................. 8 Threshold Setup and Control Registers .................................. 66 Pin Configurations and Function Descriptions ........................... 9 Clock and Timestamp Setup and Control Registers.............. 67 Typical Performance Characteristics ........................................... 13 System Registers ......................................................................... 68 Theory of Operation ...................................................................... 15 I/O Setup and Control Registers .............................................. 69 Introduction ................................................................................ 15 Time Slot Configuration Registers ........................................... 72 Analog Signal Path ..................................................................... 15 AFE Timing Setup Registers ..................................................... 76 LED Drivers ................................................................................ 16 LED Control and Timing Registers ......................................... 78 Determining C ...................................................................... 17 ADC Offset Registers ................................................................. 79 VLED Datapath, Decimation, and FIFO ............................................. 17 Output Data Registers ............................................................... 79 Clocking ....................................................................................... 19 Outline Dimensions ....................................................................... 82 Time Stamp Operation .............................................................. 19 Ordering Guide .......................................................................... 82 Low Frequency Oscillator Calibration .................................... 20 High Frequency Oscillator Calibration ................................... 20 REVISION HISTORY 6/2019Revision A: Initial Version Rev. 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