Silicon SPDT Switch, Reflective, 100 MHz to 44 GHz Data Sheet ADRF5024 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrawideband frequency range: 100 MHz to 44 GHz Reflective design Low insertion loss with impedance match ADRF5024 1.0 dB typical to 18 GHz VSS 1.4 dB typical to 40 GHz 1.7 dB typical to 44 GHz RFC Low insertion loss without impedance match CTRL 0.9 dB typical to 18 GHz 1.7 dB typical to 40 GHz VDD 2.1 dB typical to 44 GHz High input linearity P1dB: 27.5 dBm typical IP3: 50 dBm typical Figure 1. High RF input power handling Through path: 27 dBm Hot switching: 27 dBm No low frequency spurious RF settling time (50% V to 0.1 dB of final RF output): 17 ns CTRL 12-terminal, 2.25 mm 2.25 mm LGA package Pin compatible with the ADRF5025 low frequency cutoff version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5024 is a reflective, single-pole double-throw The ADRF5024 is pin-compatible with the ADRF5025, low (SPDT) switch manufactured in the silicon process. frequency cutoff version, which operates from 9 kHz to 44 GHz. This switch operates from 100 MHz to 44 GHz with better than The ADRF5024 RF ports are designed to match a characteristic 1.7 dB of insertion loss and 35 dB of isolation. The ADRF5024 impedance of 50 . For ultrawideband products, impedance has a radio frequency (RF) input power handling capability of matching on the RF transmission lines can further optimize 27 dBm for both the through path and hot switching. high frequency insertion loss and return loss characteristics. Refer to the Electrical Specifications section, Typical Performance The ADRF5024 draws a low current of 14 A on the positive Characteristics section, and Applications Information section supply of +3.3 V and 120 A on negative supply of 3.3 V. The for more details. device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)- The ADRF5024 comes in a 2.25 mm 2.25 mm, 12-terminal, compatible controls. RoHS-compliant, land grid array (LGA) package and can operate between 40C to +105C. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. RF1 RF2 DRIVER 16011-001ADRF5024 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ...................................................................................... 1 Typical Performance Characteristics .............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept ..........8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications .................................................................................... 3 Applications Information ............................................................. 10 Electrical Specifications ............................................................... 3 Evaluation Board ........................................................................ 10 Absolute Maximum Ratings ........................................................... 5 Probe Matrix Board ................................................................... 12 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13 Power Derating Curves ............................................................... 5 Ordering Guide .......................................................................... 13 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions ............................ 6 REVISION HISTORY 8/2020Rev. B to Rev. C 5/2018Rev. 0 to Rev. A Changes to Figure 7 and Figure 10 ................................................ 7 Updated Outline Dimensions ..................................................... 13 Changes to Ordering Guide .......................................................... 13 5/2020Rev. A to Rev. B Change to Return Loss Parameter, Table 1 .................................. 3 5/2018Revision 0: Initial Version Changes to Table 2 ........................................................................... 5 Changes to Insertion Loss, Return Loss, and Isolation Section, Figure 7, Figure 8, Figure 10, and Figure 11 ................................. 7 Changes to Theory of Operation Section ...................................... 9 Rev. C Page 2 of 13