Silicon SPDT Switch, Reflective, 9 kHz to 44 GHz Data Sheet ADRF5025 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrawideband frequency range: 9 kHz to 44 GHz Reflective design Low insertion loss with impedance match ADRF5025 0.9 dB typical to 18 GHz VSS 1.4 dB typical to 40 GHz 1.6 dB typical to 44 GHz RFC CTRL Low insertion loss without impedance match 0.9 dB typical to 18 GHz 1.7 dB typical to 40 GHz VDD 2.2 dB typical to 44 GHz High input linearity P1dB: 27.5 dBm typical IP3: 50 dBm typical Figure 1. High RF input power handling Through path: 27 dBm Hot switching: 27 dBm No low frequency spurious RF settling time (50% V to 0.1 dB final RF output): 3.4 s CTL 12-terminal, 2.25 mm 2.25 mm LGA package Pin compatible with the ADRF5024 fast switching version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5025 is a reflective single-pole double-throw (SPDT) The ADRF5025 is pin compatible with the ADRF5024, low switch, manufactured in silicon process. frequency cutoff version, which operates from 100 MHz to 44 GHz. This switch operates from 9 kHz to 44 GHz with better than 1.6 dB of insertion loss and 35 dB of isolation. The ADRF5025 The ADRF5025 RF ports are designed to match a characteristic has an radio frequency (RF) input power handling capability of impedance of 50 . For ultrawideband products, impedance 27 dBm for both the through path and hot switching. matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to The ADRF5025 draws a low current of 14 A on the positive the Electrical Specifications section, Typical Performance supply of +3.3 V and 120 A on negative supply of 3.3 V. The Characteristics section, and Applications Information section device employs complementary metal-oxide semiconductor for more details. (CMOS)-/low voltage transistor to transistor logic (LVTTL)- compatible controls. The ADRF5025 comes in a 2.25 mm 2.25 mm, 12-terminal, RoHS-compliant, land grid array (LGA) package and can operate from 40C to +105C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. No license is granted by implication or otherwise under any patent or patent rights of Analog Technical Support www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. RF1 RF2 DRIVER 16533-001ADRF5025 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ...................................................................................... 1 Typical Performance Characteristics .............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Return Loss, and Isolation ................................7 General Description ......................................................................... 1 Input Power Compression and Third-Order Intercept ..........8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications .................................................................................... 3 Applications Information ............................................................. 10 Electrical Specifications ............................................................... 3 Evaluation Board ........................................................................ 10 Absolute Maximum Ratings ........................................................... 5 Probe Matrix Board ................................................................... 12 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 13 Power Derating Curves ............................................................... 5 Ordering Guide .......................................................................... 13 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions ............................ 6 REVISION HISTORY 5/2020Rev. A to Rev. B 5/2018Rev. 0 to Rev. A Changes to Return Loss Parameter, Table 1 ................................. 3 Change to Input Linearity Parameter, Table 1.............................. 4 Changes to Table 2 ........................................................................... 5 Change to RF Input Power Parameter, Table 2 ............................ 5 Changes to Insertion Loss, Return Loss, and Isolation Section, Updated Outline Dimensions ...................................................... 13 Figure 7, and Figure 10 .................................................................... 7 Changes to Ordering Guide .......................................................... 13 Changes to Theory of Operation Section ...................................... 9 5/2018Revision 0: Initial Version Rev. B Page 2 of 13