Silicon SPDT Switch, Nonreflective, 100 MHz to 44 GHz Data Sheet ADRF5026 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective design Low insertion loss GND 1 15 VSS 1.2 dB to 18 GHz 50 GND 2 14 EN 1.7 dB to 26 GHz 2.4 dB to 40 GHz DRIVER RFC 3 13 GND 3.8 dB to 44 GHz 50 GND 4 12 CTRL High isolation 55 dB to 18 GHz GND 5 11 VDD 53 dB to 26 GHz 50 dB to 40 GHz 45 dB to 44 GHz High input linearity Figure 1. P1dB: 27 dBm typical IP3: 53 dBm typical High power handling 24 dBm insertion loss path 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 40 ns typical 20-terminal, 3 mm 3 mm LGA package Pin compatible with ADRF5027, low frequency cutoff version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5026 is a nonreflective, single-pole, double-throw The ADRF5026 is pin-compatible with the ADRF5027 low (SPDT) radio frequency (RF) switch manufactured in a silicon frequency cutoff version, which operates from 9 kHz to 44 GHz. process. The ADRF5026 RF ports are designed to match a characteristic The ADRF5026 operates from 100 MHz to 44 GHz with better impedance of 50 . For ultrawideband products, impedance than 3.8 dB of insertion loss and 45 dB of isolation. The ADRF5026 matching on the RF transmission lines can further optimize features an all off control, where both RF ports are in an isolation high frequency insertion loss and return loss characteristics. state. The ADRF5026 has a nonreflective design and both of the Refer to the Narrow-Band Impedance Matching section for an RF ports are internally terminated to 50 . example of a matched circuit that achieves a flat insertion loss response of 2.4 dB from 28 GHz to 43 GHz. The ADRF5026 requires a dual-supply voltage of +3.3 V and 3.3 V. The device employs complimentary metal-oxide The ADRF5026 comes in a 20-terminal, 3 mm 3 mm, RoHS- semiconductor/low-voltage transistor-transistor logic compliant, land grid array (LGA) package and can operate (CMOS/LVTTL) logic-compatible controls. from 40C to +105C. Rev. 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Trademarks and registered trademarks are the property of their respective owners. 6 20 7 19 8 18 9 17 10 16 16767-001 GND GND GND GND RF1 RF2 GND GND GND GNDADRF5026 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions .............................6 Applications ...................................................................................... 1 Interface Schematics .....................................................................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics .............................................7 General Description ......................................................................... 1 Insertion Loss, Return Loss, and Isolation ................................7 Revision History ............................................................................... 2 Input Power Compressions and Third-Order Intercept .........8 Specifications .................................................................................... 3 Theory of Operation .........................................................................9 Electrical Specifications ............................................................... 3 Applications Information ............................................................. 10 Absolute Maximum Ratings ........................................................... 5 Evaluation Board ........................................................................ 10 Thermal Resistance ...................................................................... 5 Probe Matrix Board ................................................................... 11 Power Derating Curves ............................................................... 5 Outline Dimensions ....................................................................... 13 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 13 REVISION HISTORY 9/2020Rev. 0 to Rev. A Changes to Table 2 ........................................................................... 5 Changes to Theory of Operation Section ...................................... 9 Changes to Ordering Guide .......................................................... 12 7/2018Revision 0: Initial Version Rev. A Page 2 of 13