0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz Data Sheet ADRF5720 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5720 Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.0 dB up to 18 GHz 2.8 dB up to 26 GHz 24 23 22 21 20 19 4.5 dB up to 40 GHz 1 18 LE VDD Attenuation accuracy with impedance match 2 PS 17 VSS SERIAL/ (0.20 + 1.0% of attenuation state) up to 18 GHz PARALLEL 3 16 GND GND INTERFACE (0.20 + 1.5% of attenuation state) up to 26 GHz 4 15 GND GND (0.40+ 3.0% of attenuation state) up to 40 GHz 6-BIT DIGITAL ATTIN 5 14 ATTOUT ATTENUATOR Typical step error with impedance match GND 6 13 GND 0.25 dB up to 26 GHz 7 8 9 10 11 12 0.65 dB up to 40 GHz PACKAGE BASE High input linearity P0.1dB insertion loss state: 30 dBm GND P0.1dB other attenuation states: 27 dBm Figure 1. IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8 s 24-terminal, 4 mm 4 mm LGA package Pin-compatible with ADRF5730, fast switching version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB The ADRF5720 is pin-compatible with the ADRF5730, the fast attenuation control range in 0.5 dB steps. switching version, which operates from 100 MHz to 40 GHz. This device operates from 9 kHz to 40 GHz with better than 4.5 dB The ADRF5720 RF ports are designed to match a characteristic of insertion loss and excellent attenuation accuracy. The ATTIN impedance of 50 . For wideband applications, impedance port of the ADRF5720 has a radio frequency (RF) input power matching on the RF transmission lines can further optimize high handling capability of 27 dBm average and 30 dBm peak for all frequency insertion loss, return loss, and attenuation accuracy states. characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristics section, and the Applications The ADRF5720 requires a dual supply voltage of +3.3 V and Information section for more details. 3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide The ADRF5720 comes in a 24-terminal, 4 mm 4 mm, RoHS semiconductor (CMOS)-/low voltage transistor to transistor compliant, land grid array (LGA) package and operates from logic (LVTTL)-compatible controls. 40C to +105C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 15959-001 GND D5/CLK GND D4/SERIN GND D3/SEROUT GND D2 GND D1 GND D0ADRF5720 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Applications ....................................................................................... 1 Input Power Compression and Third-Order Intercept ......... 12 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 13 General Description ......................................................................... 1 Power Sequence .......................................................................... 13 Revision History ............................................................................... 2 RF Input and Output ................................................................. 13 Specifications ..................................................................................... 3 Serial or Parallel Mode Selection ............................................. 14 Electrical Specifications ............................................................... 3 Serial Mode Interface ................................................................. 14 Timing Specifications .................................................................. 5 Parallel Mode Interface .............................................................. 15 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 16 Power Derating Curves ................................................................ 6 Evaluation Board ........................................................................ 16 ESD Caution .................................................................................. 6 Probe Matrix Board ................................................................... 18 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19 Interface Schematics..................................................................... 7 Ordering Guide .......................................................................... 19 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 11/2020Rev. A to Rev. B 3/2020Rev. 0 to Rev. A Changes to t Parameter and t Parameter, Table 2 ................. 5 Changes to RF Power Parameter, Table 1 ....................................... 5 CH CO Changes to Figure 26 and Figure 27............................................. 11 Changes to Table 3 ............................................................................. 6 Changes to Serial Mode Interface Section, Using SEROUT Section, Changes to Power Supply Section ................................................ 13 and Figure 34 ................................................................................... 14 Added Power-Up State Section..................................................... 13 Deleted Figure 33 Renumbered Sequentially ............................ 14 Moved Serial or Parallel Mode Selection Section and Table 7 Renumbered Sequentially ......................................................................14 7/2018Revision 0: Initial Version Rev. B Page 2 of 19