2 dB LSB, 4-Bit, Silicon Digital Attenuator, 9 kHz to 40 GHz Data Sheet ADRF5721 FEATURES FUNCTIONAL BLOCK DIAGRAM ADRF5721 Ultrawideband frequency range: 9 kHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.6 dB to 18 GHz 2.0 dB to 26 GHz 16 15 14 13 3.4 dB to 40 GHz D4/SERIN 1 12 VDD Attenuation accuracy SERIAL/ PARALLEL 2 11 D5/CLK VSS INTERFACE (0.1 + 1.0%) of attenuation state up to 18 GHz 10 GND 3 GND (0.1 + 2.5%) of attenuation state up to 26 GHz 4-BIT DIGITAL ATTENUATOR (0.6 + 10.0%) of attenuation state up to 40 GHz ATTIN 4 9 ATTOUT Typical step error 5 6 78 0.15 dB to 18 GHz PACKAGE BASE 0.20 dB to 26 GHz 0.60 dB to 40 GHz Figure 1. High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency switching spurs SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 8.5 s 2.5 mm 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5731, fast switching version APPLICATIONS Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs) GENERAL DESCRIPTION The ADRF5721 is a silicon, 4-bit digital attenuator with a 30 dB semiconductor (CMOS)-/low voltage transistor to transistor attenuation control range in 2 dB steps. logic (LVTTL)-compatible controls. This device operates from 9 kHz to 40 GHz with better than 3.4 dB The ADRF5721 is pin compatible with the ADRF5731, the fast of insertion loss. The ATTIN port of the ADRF5721 has a radio switching version, which operates from 100 MHz to 40 GHz. frequency (RF) input power handling capability of 26 dBm The ADRF5721 RF ports are designed to match a characteristic average and 30 dBm peak for all states. impedance of 50 . The ADRF5721 requires a dual supply voltage of +3.3 V and The ADRF5721 comes in a 16-terminal, 2.5 mm 2.5 mm, 3.3 V. The device features serial peripheral interface (SPI), RoHS compliant, land grid array (LGA) package and operates parallel mode control, and complementary metal-oxide from 40C to +105C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20182020 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. GND D3/SEROUT GND D2 PS GND GND LE 16999-001ADRF5721 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase ................................................................................8 Applications ....................................................................................... 1 Input Power Compression and Third-Order Intercept ......... 10 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Power Supply ............................................................................... 11 Revision History ............................................................................... 2 RF Input and Output ................................................................. 11 Specificat ions ..................................................................................... 3 Serial or Parallel Mode Selection ............................................. 12 Electrical Specifications ............................................................... 3 Serial Mode Interface ................................................................. 12 Timing Specifications .................................................................. 5 Parallel Mode Interface .............................................................. 13 Absolute Maximum Ratings ....................................................... 6 Applications Information .............................................................. 14 Thermal Resistance ...................................................................... 6 Evaluation Board ........................................................................ 14 Power Derating Curves ................................................................ 6 Probe Matrix Board ................................................................... 16 ESD Caution .................................................................................. 6 Packaging and Ordering Information ......................................... 17 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ................................................................... 17 Interface Schematics..................................................................... 7 Ordering Guide .......................................................................... 17 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 3/2020Rev. 0 to Rev. A Changes to RF Power Parameter, Table 1 ...................................... 4 Changes to Table 3 ............................................................................ 6 Changes to Power Supply Section ................................................ 11 Added Power-Up State Section ..................................................... 11 Moved Serial or Parallel Mode Selection Section and Table 7 Renumbered Sequentially ...................................................................... 12 9/2018Revision 0: Initial Version Rev. A Page 2 of 17