30 MHz Dual Programmable Filters and Variable Gain Amplifiers Data Sheet ADRF6510 FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL INP1 INM1 VPS COM GNSW OFS1 VPS Matched pair of programmable filters and VGAs Continuous gain control range: 5 dB to +45 dB 6-pole filter VPSD OPP1 1 MHz to 30 MHz in 1 MHz steps, 0.5 dB corner frequency COMD OPM1 SPI programmable LE COM 6 dB front-end gain step CLK GAIN SPI IMD3: >55 dBc for 1.5 V p-p composite output ADRF6510 DATA VOCM HD2, HD3: >60 dBc for 1.5 V p-p output Differential input and output SDO COM Adjustable output common-mode voltage COM OPM2 Optional dc output offset correction VPS OPP2 Power-down feature Single 5 V supply operation COM INP2 INM2 VPS COM OFDS OFS2 VPS APPLICATIONS Figure 1. Baseband I/Q receivers Diversity receivers ADC drivers GENERAL DESCRIPTION The ADRF6510 is a matched pair of fully differential low noise The variable gain amplifiers that follow the filters provide 50 dB and low distortion programmable filters and variable gain ampli- of continuous gain control with a slope of 30 mV/dB. The output fiers (VGAs). Each channel is capable of rejecting large out-of- buffers provide a differential output impedance of 20 that is band interferers while reliably boosting the wanted signal, thus capable of driving 1.5 V p-p into 1 k loads. The output common- reducing the bandwidth and resolution requirements on the mode voltage defaults to VPS/2, but it can be programmed via the analog-to-digital converters (ADCs). The excellent matching VOCM pin. The built-in dc offset correction loop can be disabled between channels and their high spurious-free dynamic range if dc-coupled operation is desired. The high-pass corner frequency is defined by external capacitors on the OFS1 and OFS2 pins. over all gain and bandwidth settings makes the ADRF6510 ideal for quadrature-based (IQ) communication systems with The ADRF6510 operates from a 4.75 V to 5.25 V supply and dense constellations, multiple carriers, and nearby interferers. consumes a maximum supply current of 258 mA when pro- The filters provide a six-pole Butterworth response with 0.5 dB grammed to the highest bandwidth setting. When disabled, it corner frequencies programmable through the SPI port from consumes 2 mA. The ADRF6510 is fabricated in an advanced 1 MHz to 30 MHz in 1 MHz steps. The preamplifier that precedes silicon-germanium BiCMOS process and is available in a the filters offers a pin-programmable option of either 6 dB or 32-lead, exposed paddle LFCSP. Performance is specified over 12 dB of gain. The preamplifier sets a differential input imped- the 40C to +85C temperature range. ance of 400 and has a common-mode voltage that defaults to 2.1 V but can be driven from 1.5 V to 2.5 V. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 0206921-06, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2010-2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 09002-001ADRF6510 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Distortion Characteristics ......................................................... 18 Applications ....................................................................................... 1 Maximizing the Dynamic Range ............................................. 18 Functional Block Diagram .............................................................. 1 Key Parameters for Quadrature-Based Receivers .................. 19 General Description ......................................................................... 1 Applications Information .............................................................. 20 Revision History ............................................................................... 2 Basic Connections ...................................................................... 20 Specifications ..................................................................................... 3 Error Vector Magnitude (EVM) Performance ........................... 20 Timing Diagrams .......................................................................... 5 EVM ............................................................................................. 21 Absolute Maximum Ratings ............................................................ 6 Effect of Filter Bandwidth on EVM ......................................... 21 ESD Caution .................................................................................. 6 Effect of Output Voltage Levels on EVM ................................ 21 Pin Configuration and Function Descriptions ............................. 7 Effect of COFS on EVM ............................................................... 22 Typical Performance Characteristics ............................................. 8 Anti-Aliasing Filter .................................................................... 22 Theory of Operation ...................................................................... 15 Evaluation Board ............................................................................ 24 Input Buffers ............................................................................... 15 Evaluation Board Control Software ......................................... 24 Programmable Filters ................................................................. 15 Schematics and Artwork ........................................................... 24 Variable Gain Amplifiers (VGAs) ............................................ 16 Evaluation Board Configuration Options ............................... 27 Output Buffers/ADC Drivers ................................................... 16 Outline Dimensions ....................................................................... 29 DC Offset Compensation Loop ................................................ 16 Ordering Guide .......................................................................... 29 Programming the Filters ............................................................ 17 Noise Characteristics ................................................................. 17 REVISION HISTORY 9/2017Rev. A to Rev. B Added EVM Section, Effect of Filter Bandwidth on EVM Changed CP-32-2 to CP-32-7 ...................................... Throughout Section, Effect of Output Voltage Levels on EVM Section, and Updated Outline Dimensions ....................................................... 29 Effect of C on EVM Section...................................................... 21 OFS Changes to Ordering Guide .......................................................... 29 Added Anti-Aliasing Filter Section .............................................. 22 Changes to Figure 54 ...................................................................... 22 10/2011Rev. 0 to Rev. A Changes to Figure 58 ...................................................................... 24 Changes to Figure 2 and Figure 3 ................................................... 5 Changes to Figure 61 ...................................................................... 25 Changes to Table 3 ............................................................................ 7 Changes to Figure 62 and Figure 63 ............................................ 26 Changes to Figure 48, Changes to Error Vector Magnitude Changes to Table 5 .......................................................................... 27 (EVM) Performance Section ......................................................... 20 Deleted Low IF Image Rejection Section, and Example 4/2010Revision 0: Initial Version Baseband Interface Section, Figure 50, and Figure 51 Renumbered Subsequent Figures ................................................. 20 Changes to Figure 49 ...................................................................... 21 Rev. B Page 2 of 32