1.1 GHz Variable Gain Amplifiers and Baseband Programmable Filters Data Sheet ADRF6518 FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL INP1 INM1 VPS RAVG VGN1 OFS1 VPS Matched pair of programmable filters and triple VGAs Continuous gain control range: 72 dB Digital gain control: 30 dB ADRF6518 Filter bypass mode bandwidth VPSD OPP1 1 dB gain flatness: 300 MHz COMD OPM1 3 dB small signal bandwidth: 650 MHz/1.1 GHz, VGA2 and VGA3 21 dB/12 dB, respectively LE COM 6-pole Butterworth filter: 1 MHz to 63 MHz CLK VGN3 in 1 MHz steps, 0.5 dB corner frequency SPI DATA VOCM Peak detector SDO/RST COM IMD3: >65 dBc for 1.5 V p-p composite output HD2, HD3: >65 dBc for 1.5 V p-p output VICM/AC OPM2 Differential input and output VPI OPP2 Flexible output and input common-mode ranges Optional dc output offset correction SPI programmable filter corners and gain steps Single 3.3 V supply operation with power-down feature COM INP2 INM2 VPS VPK VGN2 OFS2 VPS Figure 1 APPLICATIONS Point-to-point and point-to-multipoint radios Baseband IQ receivers Diversity receivers ADC drivers Instrumentation Medical GENERAL DESCRIPTION The ADRF6518 is a matched pair of fully differential low noise and A wideband peak detector is available to monitor the peak signal at low distortion programmable filters and variable gain amplifiers the filter inputs. The pair of VGAs that follow the filters each (VGAs). Each channel is capable of rejecting large out-of-band provides 24 dB of continuous gain control with fixed gain options interferers while reliably boosting the wanted signal, thus reducing of 12 dB, 15 dB, 18 dB, and 21 dB. The output buffers offer an the bandwidth and resolution requirements on the analog-to- additional option of 3 dB or 9 dB gain and provide a differential digital converters (ADCs). The excellent matching between output impedance of less than 10 . They are capable of driving 1.5 channels and their high spurious-free dynamic range over all V p-p into 400 loads at better than 65 dBc HD3. The output gain and bandwidth settings make the ADRF6518 ideal for common-mode voltage defaults to VPS/2 and can be adjusted quadrature-based (IQ) communication systems with dense down to 900 mV via the VOCM pin. Independent, built-in dc constellations, multiple carriers, and nearby interferers. The offset correction loops for each channel can be disabled via the SPI various amplifier gains, filter corners, and other features are all if fully dc-coupled operation is desired. The high-pass corner programmable via a serial port interface (SPI) port. frequency is determined by external capacitors on the OFS1 and OFS2 pins and the postfilter VGA gain. The first VGA that precedes the filters offers 24 dB of continuous gain control with fixed gain options of 9 dB, 12 dB, and 15 dB, and The ADRF6518 operates from a 3.15 V to 3.45 V supply and sets a differential input impedance of 400 . The filters provide consumes a maximum supply current of 400 mA. When fully a six-pole Butterworth response with 0.5 dB corner frequencies disabled, it consumes <1 mA. The ADRF6518 is fabricated in an from 1 MHz to 63 MHz in 1 MHz steps. For operation beyond advanced silicon-germanium BiCMOS process and is available in a 63 MHz, the filter can be disabled and completely bypassed, 32-lead, exposed pad LFCSP. Performance is specified over the thereby extending the 3 dB bandwidth (BW) up to 1.1 GHz. 40C to +85C temperature range. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 11449-001ADRF6518 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Key Parameters for Quadrature-Based Receivers .................. 25 Applications ....................................................................................... 1 Applications Information .............................................................. 26 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 26 General Description ......................................................................... 1 Supply Decoupling ..................................................................... 26 Revision History ............................................................................... 2 Input Signal Path ........................................................................ 26 Specifications ..................................................................................... 3 Output Signal Path ..................................................................... 26 Timing Diagrams .......................................................................... 5 DC Offset Compensation Loop Enabled ................................ 26 Absolute Maximum Ratings ............................................................ 6 Common-Mode Bypassing ....................................................... 27 ESD Caution .................................................................................. 6 Serial Port Connections ............................................................. 27 Pin Configuration and Function Descriptions ............................. 7 Enable/Disable Function ........................................................... 27 Typical Performance Characteristics ............................................. 8 Gain Pin Decoupling ................................................................. 27 Filter Mode .................................................................................... 8 Peak Detector Connections ...................................................... 27 Bypass Mode ............................................................................... 16 Error Vector Magnitude (EVM) Performance ........................... 27 Mixed Power and Filter Modes................................................. 18 EVM Test Setup .......................................................................... 27 Characterization ............................................................................. 19 EVM Measurement .................................................................... 27 Noise Figure Calculation ........................................................... 19 EVM System Measurement ....................................................... 29 Register Map and Codes ................................................................ 20 Effect of Filter BW on EVM ...................................................... 31 Theory of Operation ...................................................................... 21 Pull-Down Resistors for Disable Function ............................. 31 Input VGAs ................................................................................. 21 Instability at High Gain in Filter Bypass Mode ...................... 31 Peak Detector .............................................................................. 22 Instability at Low Filter Corners and Low Power Mode ....... 32 Programmable Filters ................................................................. 22 Peak Detector Bandwidth And Slew Rate ............................... 32 Variable Gain Amplifiers (VGAs) ............................................ 23 Linear Operation of the ADRF6518 ........................................ 32 Output Buffers/ADC Drivers ................................................... 23 Evaluation Board ............................................................................ 33 DC Offset Compensation Loop ................................................ 23 Evaluation Board Control Software ......................................... 33 Programming the ADRF6518 ................................................... 23 Schematics and Artwork ........................................................... 34 Noise Characteristics ................................................................. 24 Outline Dimensions ....................................................................... 39 Distortion Characteristics ......................................................... 24 Ordering Guide .......................................................................... 39 Maximizing the Dynamic Range .............................................. 25 REVISION HISTORY 12/2017Rev. 0 to Rev. A Changes to Figure 56...................................................................... 16 Changed 1100 MHz to 1.1 GHz .................................. Throughout Changes to Figure 69 and Figure 69 Caption ............................. 22 Change to Product Title ................................................................... 1 Changes to Figure 72...................................................................... 26 Changes to Figure 1 .......................................................................... 1 Changes to Figure 73 and Figure 74 ............................................ 28 Changes to Table 1 ............................................................................ 3 Added Figure 86 and Figure 87 Renumbered Sequentially .......... 32 Changes to Figure 3 .......................................................................... 5 Added Instability at Low Filter Corners and Low Power Mode Changes to Figure 12 ........................................................................ 9 Section, and Peak Detector Bandwidth and Slew Rate Section ...... 32 Changes to Figure 20 ...................................................................... 10 Changes to Figure 88 ....................................................................... 32 Reorganized Typical Performance Characteristics Section Changes to Figure 89...................................................................... 33 Renumbered Sequentially .............................................................. 10 Changes to Figure 49 Caption, Figure 51 Caption, and Figure 52 6/2013Revision 0: Initial Version Caption ............................................................................................. 15 Rev. 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