Dual Programmable Filters and VGAs for 2 GHz Channel Spacing for W Radios Data Sheet ADRF6520 FEATURES FUNCTIONAL BLOCK DIAGRAM Matched VGAs and programmable filters Maximum gain: 53 dB Continuous gain control range: 60 dB Filter bypass mode I/Q bandwidth INP1 1 24 OPP1 1 dB gain flatness: >1250 MHz INM1 2 23 OPM1 4-pole Butterworth filter I/Q bandwidth: 36 MHz to 720 MHz COM 3 22 COM ADRF6520 RMS detector CFLT1 4 21 VGN1 IMD3: <55 dBc for 1.5 V p-p composite output CFLT2 5 20 VGN2 HD2, HD3: <55 dBc for 1.5 V p-p output DETECTOR COM 6 19 COM Noise figure: 10.5 dB at maximum gain INM2 7 18 OPM2 NF < 11 dB over 12 dB of VGA2 gain backoff INP2 8 17 OPP2 100 d ifferential input, low impedance output Optional dc output offset correction SPI-programmable filter corners Single 3.3 V supply operation with power-down feature APPLICATIONS Figure 1 Point-to-point and point-to-multipoint radios Baseband IQ receivers Diversity receivers ADC drivers Instrumentation Medical GENERAL DESCRIPTION The ADRF6520 is a matched pair of fully differential low noise and up to 1.25 GHz. A wideband rms detector is available to low distortion programmable filters and variable gain amplifiers monitor the signal at the filter inputs. A fixed gain amplifier of (VGAs). Each channel is capable of rejecting large, out of band 6 dB immediately follows the filter. The postfilter VGA provides interferers while reliably boosting the wanted signal, thus reducing 30 dB of continuous gain control with a maximum gain of the bandwidth and resolution requirements on the analog-to- 12 dB. The output buffers offer an additional 18 dB of gain and provide a differential output impedance of 20 . The output digital converters (ADCs). The excellent matching between channels and their high spurious-free dynamic range over all buffers are capable of driving 1.5 V p-p into 100 l oads at better gain and bandwidth settings make the ADRF6520 ideal for than 55 dBc nominal for the third-order intermodulation quadrature-based (IQ) communication systems with dense distortion (IMD3). Independent, built in, dc offset correction constellations, multiple carriers, and nearby interferers. The loops for each channel can be disabled via the SPI if fully dc- filter corners, enable, and dc offset correction loop enable are coupled operation is desired. The high-pass corner frequency is all programmable via a serial peripheral interface (SPI). determined by external capacitors on the CHP1 and CHP2 pins and the postfilter VGA gain. The first VGA that precedes the filters offers 30 dB of continuous The ADRF6520 operates from a 3.15 V to 3.45 V supply and gain control with a maximum gain of 18 dB and sets a differential input impedance of 100 . The filters provide a four-pole consumes a maximum supply current of 425 mA. When fully Butterworth response with 1 dB corner frequencies: 36 MHz, disabled, it consumes 10 mA. The ADRF6520 is fabricated in 72 MHz, 144 MHz, 288 MHz, 432 MHz, 576 MHz, and 720 MHz. an advanced silicon-germanium BiCMOS process and is For operation beyond 720 MHz, the filter can be disabled and available in a 32-lead, exposed pad LFCSP. Performance is completely bypassed, thereby extending the 1 dB bandwidth specified over the 40C to +85C temperature range. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com RST 9 32 CS 10 31 SCLK VPSD SDIO COMD 11 30 VPS 12 29 VPS 13 28 VPS VPS COM 14 27 COM CHP2 15 26 CHP1 VRMS 16 25 ENBL 14830-001ADRF6520 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Distortion Characteristics ......................................................... 22 Applications ....................................................................................... 1 Maximizing the Dynamic Range ............................................. 22 Functional Block Diagram .............................................................. 1 Key Parameters for Quadrature-Based Receivers .................. 23 General Description ......................................................................... 1 SPI Register and Timing ................................................................ 24 Revision History ............................................................................... 2 Register Read/Write Timing ..................................................... 25 Specifications ..................................................................................... 3 Applications Information .............................................................. 26 Absolute Maximum Ratings ............................................................ 6 Basic Connections ...................................................................... 26 Thermal Resistance ...................................................................... 6 Supply Decoupling ..................................................................... 26 ESD Caution .................................................................................. 6 Input Signal Path ........................................................................ 26 Pin Configuration and Function Descriptions ............................. 7 Output Signal Path ..................................................................... 26 Typical Performance Characteristics ............................................. 8 DC Offset Compensation Loop Enabled ................................ 26 Theory of Operation ...................................................................... 19 Serial Port Connections ............................................................. 26 Input VGAs ................................................................................. 19 Enable/Disable Function ........................................................... 27 RMS Detector .............................................................................. 19 Gain Pin Decoupling ................................................................. 27 Programmable Filters ................................................................. 20 RMS Detector Connections ...................................................... 27 Variable Gain Amplifiers ........................................................... 20 VGA2 Gain step response ......................................................... 27 Output Buffers/ADC Drivers ................................................... 20 Linear Operation of the ADRF6520 ........................................ 27 DC Offset Compensation Loop ................................................ 21 Evaluation Board ............................................................................ 28 Programming the ADRF6520 ................................................... 21 Outline Dimensions ....................................................................... 29 Noise Characteristics ................................................................. 21 Ordering Guide .......................................................................... 29 REVISION HISTORY 4/2017Revision 0: Initial Version Rev. 0 Page 2 of 29