1000 MHz to 3100 MHz Rx Mixer with Integrated Fractional-N PLL and VCO Data Sheet ADRF6602 The PLL can support input reference frequencies from 12 MHz FEATURES to 160 MHz. The PFD output controls a charge pump whose Rx mixer with integrated fractional-N PLL output drives an off-chip loop filter. RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz The loop filter output is then applied to an integrated VCO. The Input P1dB: 14.8 dBm VCO output at 2 f is applied to an LO divider, as well as to a LO Input IP3: 30 dBm programmable PLL divider. The programmable PLL divider is IIP3 optimization via external pin controlled by a - modulator (SDM). The modulus of the SDM SSB noise figure can be programmed from 1 to 2047. IP3SET pin open: 13.8 dB The active mixer converts the single-ended 50 RF input to IP3SET pin at 3.3 V: 15 dB a 200 differential IF output. The IF output can operate up Voltage conversion gain: 6.5 dB to 500 MHz. Matched 200 IF output impedance The ADRF6602 is fabricated using an advanced silicon-germanium IF 3 dB bandwidth: 500 MHz BiCMOS process. It is available in a 40-lead, RoHS-compliant, Programmable via 3-wire SPI interface 6 mm 6 mm LFCSP with an exposed paddle. Performance is 40-lead, 6 mm 6 mm LFCSP specified over the 40C to +85C temperature range. APPLICATIONS Table 1. Cellular base stations Internal LO 3 dB RFIN 1 dB RFIN GENERAL DESCRIPTION Part No. Range Balun Range Balun Range ADRF6601 750 MHz 300 MHz 450 MHz The ADRF6602 is a high dynamic range active mixer with 1160 MHz 2500 MHz 1600 MHz integrated phase-locked loop (PLL) and voltage controlled ADRF6602 1550 MHz 1000 MHz 1350 MHz oscillator (VCO). The PLL/synthesizer uses a fractional-N 2150 MHz 3100 MHz 2750 MHz PLL to generate a fLO input to the mixer. The reference input ADRF6603 2100 MHz 1100 MHz 1450 MHz can be divided or multiplied and then applied to the PLL phase frequency detector (PFD). 2600 MHz 3200 MHz 2850 MHz ADRF6604 2500 MHz 1200 MHz 1600 MHz 2900 MHz 3600 MHz 3200 MHz FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC LO VCC MIX VCC V2I VCC LO NC NC 1 10 17 22 27 34 32 33 ADRF6602 36 LODRV EN 3.3V INTERNAL LO RANGE 2 DECL3P3 LDO 1550MHz TO 2150MHz LON 37 BUFFER 2.5V 9 DECL2P5 38 LDO LOP BUFFER PLL EN 16 DIV VCO 40 2:1 DECLVCO BY LDO FRACTION INTEGER MUX 12 DATA MODULUS 2, 1 REG REG SPI 13 CLK INTERFACE LE 14 26 RF IN THIRD-ORDER FRACTIONAL VCO INTERPOLATOR 29 IP3SET CORE 2 N COUNTER PRESCALER 21 TO 123 2 6 REF IN MUX CHARGE PUMP 2 250A, PHASE + FREQUENCY 500A (DEFAULT), TEMP 4 DETECTOR 750A, SENSOR 1000A 8 MUXOUT 4 7 11 15 20 21 23 24 25 28 30 31 35 5 39 18 19 3 R CP VTUNE IFP IFN SET GND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20102013 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 08545-001ADRF6602 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 3- Modulator Dither Control (Default: 0x10000B) .................................................................................... 17 Applications ....................................................................................... 1 Register 4PLL Charge Pump, PFD, and Reference Path General Description ......................................................................... 1 Control (Default: 0x0AA7E4) ................................................... 18 Functional Block Diagram .............................................................. 1 Register 5PLL Enable and LO Path Control (Default: Revision History ............................................................................... 2 0x0000E5) .................................................................................... 19 Specifications ..................................................................................... 3 Register 6VCO Control and VCO Enable (Default: RF Specifications .......................................................................... 3 0x1E2106) .................................................................................... 19 Synthesizer/PLL Specifications ................................................... 4 Register 7Mixer Bias Enable and External VCO Enable (Default: 0x000007) .................................................................... 19 Logic Input and Power Specifications ....................................... 4 Theory of Operation ...................................................................... 20 Timing Characteristics ................................................................ 5 Programming the ADRF6602 ................................................... 20 Absolute Maximum Ratings ............................................................ 6 Initialization Sequence .............................................................. 20 ESD Caution .................................................................................. 6 LO Selection Logic ..................................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Applications Information .............................................................. 22 Typical Performance Characteristics ............................................. 9 Basic Connections for Operation ............................................. 22 RF Frequency Sweep .................................................................... 9 AC Test Fixture ............................................................................... 23 IF Frequency Sweep ................................................................... 10 Evaluation Board ............................................................................ 24 Spurious Performance................................................................ 15 Evaluation Board Control Software ......................................... 24 Register Structure ........................................................................... 16 Schematic and Artwork ............................................................. 26 Register 0Integer Divide Control (Default: 0x0001C0)..... 16 Evaluation Board Configuration Options ............................... 28 Register 1Modulus Divide Control (Default: 0x003001) .. 16 Outline Dimensions ....................................................................... 29 Register 2Fractional Divide Control (Default: 0x001802) 17 Ordering Guide .......................................................................... 29 REVISION HISTORY 10/13Rev. C to Rev. D Changes to Figure 20 ...................................................................... 14 Changed 1550 MHz to 2150 MHz to 1000 MHz to Changes to Figure 21 ...................................................................... 17 3100 MHz in Product Title ............................................................ 1 Changes to Figure 22 ...................................................................... 18 Updated Outline Dimensions ....................................................... 29 Changes to Figure 23 ...................................................................... 19 9/10Rev. B to Rev. C 4/10Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Table 1 ....................................................................................1 Changes to Table 2 ............................................................................ 3 Changes to Figure 1 ........................................................................... 1 Changes to Table 3 and Table 4 ....................................................... 4 Change to Synthesizer/PLL Specifications Section ....................... 4 Changes to Table 6 ............................................................................ 6 Change to Table 3 .............................................................................. 4 Changes to Typical Performance Characteristics Section ........... 9 Changes to Initializing Sequence Section ................................... 15 Added Spurious Performance Section ......................................... 15 Changes to Figure 16 ...................................................................... 12 Changes to Programming the ADRF6602 Section .................... 20 Changes to Figure 17 ...................................................................... 13 Added AC Test Fixture Section and Figure 47 ........................... 23 Changes to Figure 19 ...................................................................... 14 Changes to Evaluation Board Control Software Section ........... 24 Changes to Figure 21 ...................................................................... 17 Changes to Figure 24 ...................................................................... 20 7/10Rev. A to Rev. B 1/10Revision 0: Initial Version Changes to Table 1 ............................................................................ 1 Changes to Table 6 ............................................................................ 6 Rev. D Page 2 of 32