700 MHz to 3000 MHz Dual Passive Receive Mixer with Integrated PLL and VCO Data Sheet ADRF6612 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency: 700 MHz to 3000 MHz, continuous LO input frequency: 200 MHz to 2700 MHz, high-side or low- side injection 2 46 45 44 48 47 43 42 39 38 41 40 37 IF range: 40 MHz to 500 MHz GND 1 34 VCC10 33 VCC9 GND 3 PLL REF BUFFER Power conversion gain of 9.0 dB VCO PFD/CP 32 VCC8 GND 6 FRACTIONAL DIVIDER Single sideband (SSB) noise figure of 11.3 dB VCO VCC1 7 36 RFBCT1 Input IP3 of 30 dBm 35 RFIN1 VCO Input P1dB of 10.6 dBm 31 VCC7 1 TO EXTVCOIN+ 4 Typical LO input drive of 0 dBm 32 30 LDO2 EXTVCOIN 5 26 Single-ended, 50 RF port RFIN2 ADRF6612 8 DECL1 25 RFBCT2 PLL Single-ended or balanced LO input port VCO DECL2 9 3.3V LDO LDO 29 VCC6 Serial port interface (SPI) control on all functions 10 SPI DECL3 CONTROL SPI DIV 28 VCC5 11 DECL4 2.5V 3.3V Exposed pad, 7 mm 7 mm, 48-lead LFCSP LDO LDO 27 VCC4 12 DECL5 13 14 15 16 17 18 19 22 23 20 21 24 APPLICATIONS Multiband/multistandard cellular base station diversity receivers Figure 1. Wideband radio link diversity downconverters Multimode cellular extenders and picocells GENERAL DESCRIPTION The ADRF6612 is a dual radio frequency (RF) mixer and wideband applications where in band blocking signals may intermediate frequency (IF) amplifier with an integrated phase- otherwise result in the degradation of dynamic range. Noise locked loop (PLL) and voltage controlled oscillators (VCOs). The performance under blocking is comparable to narrow-band ADRF6612 uses revolutionary broadband square wave limiting passive mixer designs. High linearity IF buffer amplifiers follow the local oscillator (LO) amplifiers to achieve an unprecedented RF passive mixer cores, yielding typical power conversion gains of bandwidth of 700 MHz to 3000 MHz. Unlike narrow-band sine 9 dB, and can be matched to a wide range of output impedances. wave LO amplifier solutions, the LO can be applied above or The PLL architecture supports both integer-N and fractional-N below the RF input over an extremely wide bandwidth. Energy operation and can generate the entire LO frequency range of storage elements are not utilized in the LO amplifier, thus dc 200 MHz to 2700 MHz using an external reference input current consumption also decreases with decreasing LO frequency anywhere in the range of 12 MHz to 320 MHz. An frequency. external loop filter provides flexibility in trading off phase noise The ADRF6612 utilizes highly linear, doubly balanced passive vs. acquisition time. To reduce fractional spurs in fractional-N mixer cores with integrated RF and LO balancing circuits to mode, a sigma-delta (-) modulator controls the post-VCO allow single-ended operation. Integrated RF baluns allow optimal programmable divider. The VCO consists of multiple VCO cores. performance over the 700 MHz to 3000 MHz RF input frequency. All features of the ADRF6612 are controlled via a 3-wire SPI The balanced passive mixer arrangement provides outstanding resulting in optimum performance and minimum external LO to RF and LO to IF leakages, excellent RF to IF isolation, components. and excellent intermodulation performance over the full RF The ADRF6612 is fabricated using a BiCMOS, high performance bandwidth. IC process. The device is available in a 7 mm 7 mm, 48-lead The balanced mixer cores provide extremely high input LFCSP package and operates over a 40C to +85C temperature linearity, allowing the device to be used in demanding range. An evaluation board is available. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20142016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com VCOVTUNE VCC12 MUX LDO4 LOOUT+ LDO3 LOOUT GND LDO1 CPOUT VCC2 REFIN SDIO MUXOUT SCLK CS IFOUT+ IFOUT2+ IFOUT2 IFOUT VCC11 VCC3 DNC DNC GND GND 12199-001ADRF6612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Spurious Performance ............................................................... 29 Applications ....................................................................................... 1 Circuit Description......................................................................... 31 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 31 General Description ......................................................................... 1 External LO Generation ............................................................ 31 Revision History ............................................................................... 2 Internal LO Generation ............................................................. 31 Specif icat ions ..................................................................................... 3 Applications Information .............................................................. 35 RF Specifications .......................................................................... 3 Basic Connections Pin Description ............................................. 36 Synthesizer/PLL Specifications ................................................... 4 Mixer Optimization ....................................................................... 37 VCO Specifications, Open-Loop ................................................ 7 RF Input Balun Insertion Loss Optimization ......................... 37 Logic Input and Power Specifications ....................................... 8 IIP3 Optimization ...................................................................... 37 Digital Logic Specifications ......................................................... 9 VGS Programming ..................................................................... 38 Absolute Maximum Ratings .......................................................... 10 Low-Pass Filter Programming .................................................. 38 Thermal Resistance .................................................................... 10 Register Summary .......................................................................... 40 ESD Caution ................................................................................ 10 Register Details ............................................................................... 41 Pin Configuration and Function Descriptions ........................... 11 Evaluation Board ............................................................................ 52 Typical Performance Characteristics ........................................... 13 Outline Dimensions ....................................................................... 57 Mixer, High Performance Mode ............................................... 13 Ordering Guide .......................................................................... 57 Mixer, High Efficiency Mode .................................................... 22 Synthesizer ................................................................................... 23 REVISION HISTORY 5/2016Rev. 0 to Rev. A Changes to Table 19 ........................................................................ 32 Changes to Address: 0x22, Reset: 0x000A, Name: VCO CTRL1 Section and Table 34 ....................................................................... 45 Updated Outline Dimensions ....................................................... 57 Changes to Ordering Guide .......................................................... 57 12/2014Revision 0: Initial Version Rev. A Page 2 of 57