700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO Data Sheet ADRF6614 FEATURES FUNCTIONAL BLOCK DIAGRAM RF frequency: 700 MHz to 3000 MHz, continuous LO input frequency: 200 MHz to 2700 MHz, high-side or low- side injection 2 46 45 44 48 47 43 42 39 38 41 40 37 1 34 GND VCC10 IF range: 40 MHz to 500 MHz 33 VCC9 GND 3 PLL REF BUFFER Power conversion gain of 9.0 dB VCO PFD/CP 32 VCC8 6 GND FRACTIONAL DIVIDER Phase noise performance of 144 dBc/Hz at 800 kHz offset VCO VCC1 7 36 RFBCT1 supporting stringent GSM standards in both 800 MHz to 35 RFIN1 VCO 31 VCC7 900 MHz and 1800 MHz to 1900 MHz bands 1 TO 4 EXTVCOIN+ 32 30 LDO2 Single-sideband (SSB) noise figure of 11.3 dB EXTVCOIN 5 26 RFIN2 ADRF6614 Input IP3 of 30 dBm 8 25 DECL1 RFBCT2 PLL VCO 9 3.3V DECL2 Input P1dB of 10.6 dBm LDO LDO 29 SPI VCC6 10 DECL3 SPI DIV CONTROL Typical LO input drive of 0 dBm 28 VCC5 DECL4 11 2.5V 3.3V LDO LDO 27 VCC4 12 DECL5 Single-ended, 50 RF port 13 14 15 16 17 18 19 22 23 20 21 24 Single-ended or balanced LO input port Serial port interface (SPI) control on all functions Exposed pad, 7 mm 7 mm, 48-lead LFCSP Figure 1. APPLICATIONS Multiband/multistandard cellular base station diversity receivers Wideband radio link diversity downconverters Multimode cellular extenders and picocells IF buffer amplifiers follow the passive mixer cores, yielding GENERAL DESCRIPTION typical power conversion gains of 9.0 dB, and can be matched The ADRF6614 is a dual radio frequency (RF) mixer and to a wide range of output impedances. intermediate frequency (IF) amplifier with an integrated phase- The PLL architecture supports both integer-N and fractional-N locked loop (PLL) and voltage controlled oscillators (VCOs). The operation and can generate the entire LO frequency range of ADRF6614 uses revolutionary broadband square wave limiting 200 MHz to 2700 MHz using an external reference input frequency local oscillator (LO) amplifiers to achieve a wideband RF bandwidth anywhere in the range of 12 MHz to 320 MHz. An external loop of 700 MHz to 3000 MHz. Unlike narrow-band sine wave LO filter provides flexibility in trading off phase noise vs. acquisition amplifier solutions, the LO can be applied above or below the RF time. To reduce fractional spurs in fractional-N mode, a - input over a wide bandwidth. Energy storage elements are not modulator controls the post VCO-programmable divider. The utilized in the LO amplifier, thus dc current consumption also device integrates six VCO cores, four of which provide complete decreases with decreasing LO frequency. frequency coverage between 200 MHz and 2700 MHz, and meet The ADRF6614 utilizes highly linear, doubly balanced passive the GSM phase noise requirements in the 800 MHz and 900 MHz mixer cores with integrated RF and LO balancing circuits to bands. Two additional GSM only cores enable the ADRF6614 to allow single-ended operation. Integrated RF baluns allow optimal meet the GSM phase noise requirements in the digital cellular performance over the 700 MHz to 3000 MHz RF input frequency. system 1800 MHz (DCS1800) and personal communications The balanced passive mixer arrangement provides outstanding LO service 1900 MHz (PCS1900) bands. to RF and LO to IF leakages, excellent RF to IF isolation, and All features of the ADRF6614 are controlled via a 3-wire SPI, excellent intermodulation performance over the full RF bandwidth. resulting in optimum performance and minimum external The balanced mixer cores provide extremely high input linearity, components. allowing the device to be used in demanding wideband applications The ADRF6614 is fabricated using a BiCMOS, high performance where in-band blocking signals may otherwise result in the degra- IC process. The device is available in a 7 mm 7 mm, 48-lead dation of dynamic range. Noise performance under blocking is LFCSP package and operates over a 40C to +85C temperature comparable to narrow-band passive mixer designs. High linearity range. An evaluation board is available. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com VCOVTUNE VCC12 MUX LDO4 LOOUT+ LDO3 LOOUT GND LDO1 CPOUT VCC2 REFIN SDIO MUXOUT SCLK CS IFOUT+ IFOUT2+ IFOUT2 IFOUT VCC11 VCC3 DNC DNC GND GND 14115-001ADRF6614 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Spurious Performance ............................................................... 32 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 34 Functional Block Diagram .............................................................. 1 RF Subsystem .............................................................................. 34 General Description ......................................................................... 1 External LO Generation ............................................................ 34 Revision History ............................................................................... 2 Internal LO Generation ............................................................. 34 Specifications ..................................................................................... 3 Applications Information .............................................................. 38 RF Specifications .......................................................................... 3 Basic Connections by Pin Description ........................................ 39 Synthesizer/PLL Specifications ................................................... 4 Mixer Optimization ....................................................................... 40 VCO Specifications, Open-Loop ................................................ 7 RF Input Balun Insertion Loss Optimization ......................... 40 Logic Input and Power Specifications ....................................... 8 IIP3 Optimization ...................................................................... 40 Digital Logic Specifications ......................................................... 9 VGS Programming ..................................................................... 41 Absolute Maximum Ratings .......................................................... 10 Low-Pass Filter Programming .................................................. 41 Thermal Resistance .................................................................... 10 GSM Mode of Operation........................................................... 43 ESD Caution ................................................................................ 10 Register Summary .......................................................................... 44 Pin Configuration and Function Descriptions ........................... 11 Register Details ............................................................................... 45 Typical Performance Characteristics ........................................... 13 Evaluation Board ............................................................................ 55 Mixer, High Performance Mode ............................................... 13 Outline Dimensions ....................................................................... 61 Mixer, High Efficiency Mode .................................................... 22 Ordering Guide .......................................................................... 61 Synthesizer ................................................................................... 23 REVISION HISTORY 3/16Revision 0: Initial Version Rev. 0 Page 2 of 61