700 MHz to 2700 MHz Rx Mixer with Integrated IF DGA, Fractional-N PLL, and VCO Data Sheet ADRF6620 FEATURES FUNCTIONAL BLOCK DIAGRAM Integrated fractional-N phase-locked loop (PLL) RF input frequency range: 700 MHz to 2700 MHz Internal local oscillator (LO) frequency range: 350 MHz to IFOUT1 IFOUT1+ 2850 MHz RFIN0 IFOUT2 RFIN1 Input P1dB: 17 dBm IFOUT2+ RFIN2 RFIN3 Output IP3: 45 dBm LOIN+ Single-pole four-throw (SP4T) RF input switch LOIN 8 1, 2, 4 CP PFD CHARGE Digital step attenuator (DSA) range: 0 dB to 15 dB REFIN 4, 8 + PUMP 2 VTUNE Integrated RF tunable balun allowing single-ended 50 i nput 1 2 Multicore integrated voltage controlled oscillator (VCO) LOIN+ LOIN Digitally programmable variable gain amplifier (DGA) FRAC 2 VTUNE N = INT + MOD 3 dB bandwidth: >600 MHz CP SERIAL Balanced 150 IF output impedance MUXOUT LDO PORT LDO LDO LOCK DET 2.5 V INTERFACE VCO 3.3V VPTAT Programmable via 3-wire serial port interface (SPI) Single 5 V supply APPLICATIONS Figure 1. Wireless receivers Digital predistortion (DPD) receivers GENERAL DESCRIPTION The ADRF6620 is a highly integrated active mixer and synthesizer The ADRF6620 offers two alternatives for generating the dif- that is ideally suited for wireless receiver subsystems. The feature ferential LO input signal: externally, via a high frequency, low rich device consists of a high linearity broadband active mixer phase noise LO signal, or internally, via the on-chip fractional-N an integrated fractional-N PLL low phase noise, multicore VCO PLL synthesizer. The integrated synthesizer enables continuous and IF DGA. In addition, the ADRF6620 integrates a 4:1 RF LO coverage from 350 MHz to 2850 MHz. The PLL reference switch, an on-chip tunable RF balun, programmable RF attenuator, input can support a wide frequency range because the divide and and low dropout (LDO) regulators. This highly integrated device multiply blocks can be used to increase or decrease the reference frequency to the desired value before it is passed to the phase fits within a small 7 mm 7 mm footprint. frequency detector (PFD). The high isolation 4:1 RF switch and on-chip tunable RF balun enable the ADRF6620 to support four single-ended 50 The integrated high linearity DGA provides an additional gain terminated RF inputs. A programmable attenuator ensures range from 3 dB to 15 dB in steps of 0.5 dB for maximum flexibility optimal RF input drive to the high linearity mixer core. The in driving an analog-to-digital converter (ADC). integrated DSA has an attenuation range of 0 dB to 15 dB with The ADRF6620 is fabricated using an advanced silicon-germanium a step size of 1 dB. BiCMOS process. It is available in a 48-lead, RoHS-compliant, 7 mm 7 mm LFCSP package with an exposed pad. Performance is specified over the 40C to +85C temperature range. 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Technical Support www.analog.com RFSW0 RFSW1 DECL2 MXOUT+ CS MXOUT SCLK IFIN+ SDIO IFIN DECL4 DECL1 11489-001ADRF6620 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Port Interface (SPI) ......................................................... 27 Applications ....................................................................................... 1 Basic Connections ...................................................................... 28 Functional Block Diagram .............................................................. 1 RF Input Balun Insertion Loss Optimization ......................... 30 General Description ......................................................................... 1 IP3 and Noise Figure Optimization ......................................... 31 Revision History ............................................................................... 2 Interstage Filtering Requirements ............................................ 35 Specifications ..................................................................................... 3 IF DGA vs. Load ......................................................................... 38 RF Input to IF DGA Output System Specifications ................. 3 ADC Interfacing ......................................................................... 39 Synthesizer/PLL Specifications ................................................... 4 Power Modes ............................................................................... 40 RF Input to Mixer Output Specifications .................................. 6 Layout .......................................................................................... 40 IF DGA Specifications ................................................................. 7 Register Map ................................................................................... 41 Digital Logic Specifications ......................................................... 8 Register Address Descriptions ...................................................... 42 Absolute Maximum Ratings ............................................................ 9 Register 0x00, Reset: 0x00000, Name: SOFT RESET ........... 42 Thermal Resistance ...................................................................... 9 Register 0x01, Reset: 0x8B7F, Name: Enables ........................ 42 ESD Caution .................................................................................. 9 Register 0x02, Reset: 0x0058, Name: INT DIV ..................... 43 Pin Configuration and Function Descriptions ........................... 10 Register 0x03, Reset: 0x0250, Name: FRAC DIV ................. 43 Typical Performance Characteristics ........................................... 11 Register 0x04, Reset: 0x0600, Name: MOD DIV .................. 43 RF Input to DGA Output System Performance ..................... 11 Register 0x20, Reset: 0x0C26, Name: CP CTL ...................... 44 Phase-Locked Loop (PLL) ......................................................... 13 Register 0x21, Reset: 0x0003, Name: PFD CTL .................... 45 RF Input to Mixer Output Performance ................................. 17 Register 0x22, Reset: 0x000A, Name: FLO CTL ................... 46 IF DGA ........................................................................................ 20 Register 0x23, Reset: 0x0000, Name: DGA CTL................... 47 Spurious Performance................................................................ 22 Register 0x30, Reset: 0x00000, Name: BALUN CTL ............ 48 Theory of Operation ...................................................................... 24 Register 0x31, Reset: 0x08EF, Name: MIXER CTL .............. 48 RF Input Switches ....................................................................... 24 Register 0x40, Reset: 0x0010, Name: PFD CTL2 .................. 49 Tunable Balun ............................................................................. 25 Register 0x42, Reset: 0x000E, Name: DITH CTL1 ............... 50 RF Digital Step Attenuator (DSA) ............................................ 25 Register 0x43, Reset: 0x0001, Name: DITH CTL2 ............... 50 Active Mixer ................................................................................ 25 Outline Dimensions ....................................................................... 51 Digitally Programmable Variable Gain Amplifier (DGA) .... 25 Ordering Guide .......................................................................... 51 LO Generation Block ................................................................. 26 REVISION HISTORY 7/13Revision 0: Initial Version Rev. 0 Page 2 of 52