Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO Data Sheet ADRF6655 The programmable divider is controlled by an - modulator FEATURES (SDM). The modulus of the SDM can be programmed between Broadband active mixer with integrated fractional-N PLL 1 and 2047. RF input frequency range: 100 MHz to 2500 MHz Internal LO frequency range: 1050 MHz to 2300 MHz The broadband, active mixer employs a bias adjustment to allow Flexible IF output interface for enhanced IP3 performance at the expense of increased supply Input P1dB: 12 dBm current. The mixer provides an input IP3 exceeding 25 dBm Input IP3: 29 dBm with 12 dB single sideband NF under typical conditions. The IIP3 Noise figure (SSB): 12 dB can be boosted to ~29 dBm with roughly 20 mA of additional Voltage conversion gain: 6 dB supplied current. The mixer provides a typical voltage conversion Matched 200 output impedance gain of 6 dB with a 200 differential IF output impedance. The SPI serial interface for PLL programming IF output can be externally matched to support upconversion over 40-lead 6 mm 6 mm LFCSP a limited frequency range. The ADRF6655 is fabricated using an advanced silicon- germanium BiCMOS process. It is packaged in a 40-lead, GENERAL DESCRIPTION exposed-paddle, Pb-free, 6 mm 6 mm LFCSP. Performance is The ADRF6655 is a high dynamic range active mixer with specified over a 40C to +85C temperature range. integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 f is then applied to a local LO oscillator (LO) divider as well as to a programmable PLL divider. FUNCTIONAL BLOCK DIAGRAM GND GND VCCLO NC NC GND 36 33 35 34 32 31 30 GND LOSEL LON 37 29 IP3SET ADRF6655 BUFFER 28 GND LOP 38 27 VCCMIX BUFFER INTEGER FRACTION 26 INP DIVIDER MODULUS MUX GND 11 REG REG 2 OR 3 25 INN DATA 12 LOSEL SPI THIRD-ORDER CLK 13 INTERFACE FRACTIONAL LE 14 INTERPOLATOR VCO GND 15 N COUNTER 24 PRESCALER GND CORE 21 TO 123 2 23 GND REFIN 6 PHASE MUX + CHARGE PUMP 22 VCCV2I FREQUENCY 2 TEMP 7 DETECTOR 250A, GND SENSOR 21 500A (DEFAULT), GND 4 750A, 3.3V LDO 2.5V LDO VCO LDO 1000A MUXOUT 8 1 2 3 4 5 9 10 39 40 16 17 18 19 20 VCC1 DECL1 CP GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. 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Technical Support www.analog.com 08817-001ADRF6655 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Matching and Biasing .................................................. 19 General Description ......................................................................... 1 Input Matching ........................................................................... 20 Functional Block Diagram .............................................................. 1 IP3SET Linearization Feature ................................................... 21 Revision History ............................................................................... 2 CDAC Linearization Feature .................................................... 21 Specifications ..................................................................................... 3 External LO Interface ................................................................ 21 Timing Characteristics ................................................................ 5 Using an External VCO ............................................................. 22 Absolute Maximum Ratings ............................................................ 6 ADRF6655 Control Software ........................................................ 23 ESD Caution .................................................................................. 6 PLL Loop Filter Design ............................................................. 23 Pin Configuration and Function Despcriptions .......................... 7 Register Structure ........................................................................... 24 Typical Performance Characteristics ............................................. 9 Device Programming ................................................................. 25 Downconversion ........................................................................... 9 Initialization Sequence .............................................................. 25 Upconversion .............................................................................. 11 Register 0Integer Divide Control ......................................... 26 PLL Characteristic ...................................................................... 12 Register 1Modulus Divide Control ...................................... 27 Complimentary Cumulative Distribution Function (CCDF): Register 2Fractional Divide Control .................................... 27 Downconversion, LO = 1100 MHz, RF = 900 MHz .............. 14 Register 3- Modulator Dither Control ........................... 28 Complimentary Cumulative Distribution Function (CCDF): Register 4Charge Pump, PFD, and Reference Downconversion, LO = 1700 MHz, RF = 1900 MHz ............ 15 Path Control ................................................................................ 29 Complimentary Cumulative Distribution Function (CCDF): Register 5LO Path and Mixer Control ................................. 31 Upconversion Distribution ....................................................... 16 Register 6VCO Control and PLL Enables ........................... 32 Circuit Description ......................................................................... 17 Register 7External VCO Control ......................................... 33 PLL and VCO Block ................................................................... 17 Characterization Setups ................................................................. 34 RF Mixer Block ........................................................................... 17 Evaluation Board Layout and Thermal Grounding ................... 38 Digital Interfaces ........................................................................ 18 Outline Dimensions ....................................................................... 41 Analog Interfaces ............................................................................ 19 Ordering Guide .......................................................................... 41 Supply Connections ................................................................... 19 Synthesizer Connections ........................................................... 19 REVISION HISTORY 9/14Rev. 0 to Rev. A Changes to Figure 3 .......................................................................... 7 Changes to Table 4 ............................................................................ 8 Changes to ADRF6655 Control Software Section, Figure 66, and Figure 67 ................................................................................... 23 Updated Outline Dimensions ....................................................... 41 2/10Revision 0: Initial Version Rev. A Page 2 of 41