Wideband, Dual Rx Mixers with Integrated IF Amplifiers Data Sheet ADRF6658 FEATURES GENERAL DESCRIPTION Wideband, dual-channel, active downconversion mixers The ADRF6658 is a high performance, low power, wideband, Low distortion, fast settling, IF DGAs dual-channel radio frequency (RF) downconverter with RF input frequency range: 690 MHz to 3.8 GHz integrated intermediate frequency (IF) digitally controlled Programmable baluns on RF inputs amplifiers (DGAs) for wideband, low distortion base station For RF = 1950 MHz, IF = 281 MHz, high linearity mode radio receivers. Voltage conversion gain, including IF filter loss: The dual Rx mixers are doubly balanced Gilbert cell mixers 5 dB to +26.5 dB with high linearity and excellent image rejection. Both mixers Input IP3: 29 dBm at minimum DGA gain convert 50 RF inputs to open -collector broadband IF outputs. Input P1dB: 12 dBm at minimum DGA gain Internal tunable baluns on the RF inputs enable suppression of SSB NF: 13 dB at maximum DGA gain RF signal harmonics and attenuation of out-of-band signals Output IP3: 40 dBm at maximum DGA gain before the mixer inputs, reducing input reflections and out-of- Output P1dB: 19 dBm at maximum DGA gain band interference signals. A flexible local oscillator (LO) Channel isolation: 52 dB architecture allows the use of differential or single-ended LO Differential and single-ended LO input modes signals. Differential IF output impedance: 100 The dual-channel IF DGAs are based on the ADL5201 and Flexible power-down modes for low power operation ADL5202 and have a fixed, differential output impedance of Power-up time after enabling channels: 100 ns, typical 100 . The gain is adjustable over a 31.5 dB range with a 0.5 dB Programmable via a 3-wire serial port interface (SPI) step size via the on-chip SPI, or through independent, 6-bit Single 3.3 V supply parallel ports that support latch functionality. Each channel, High linearity mode: 440 mA from the mixer inputs to the IF amplifier outputs, together with Low power mode: 260 mA an LC interstage band-pass filter, achieves a maximum voltage APPLICATIONS conversion gain of 26.5 dB. Cellular base stations and wireless infrastructure receivers Fabricated with the Analog Devices, Inc., high speed SiGe (W-CDMA, TD-SCDMA, WiMAX, GSM, LTE, PCS, DCS, DECT) process, the ADRF6658 is available in a compact, 7 mm Active antenna systems 7 mm, 48-lead LFCSP package, and operates over the 40C to PTP radio link down converters +105C temperature range. Wireless LANs and CATV equipment FUNCTIONAL BLOCK DIAGRAM LOV MIX V MIX OUT+ MIX OUT CH EN DGA IN DGA IN+ LATCH A0 TO A5 DGA V DV A A DD A DD A A A A A DD DD MIX RF A IN IF OUT+ LATCH A A +22dB 100 IF OUT A MIXA 0dB TO 31.5dB SDO DATA CONTROL LO + IN ADRF6658 CLK REGISTERS LO IN LE 0dB TO 31.5dB MIX RF B IN MIXB IF OUT+ B +22dB 100 LATCH B IF OUT B MIX V MIX OUT+ MIX OUT CH EN DGA IN DGA IN+ LATCH B0 TO B5 DGA V AGND B DD B B B B B B B DD Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2015 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Technical Support www.analog.com Trademarks and registered trademarks are the property of their respective owners. 12223-001ADRF6658 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register 5 ..................................................................................... 19 Applications ....................................................................................... 1 Register 6 ..................................................................................... 20 General Description ......................................................................... 1 Register 7 ..................................................................................... 21 Functional Block Diagram .............................................................. 1 Register 8 Through Register 12 ................................................ 22 Revision History ............................................................................... 2 Register 13 ................................................................................... 23 Specifications ..................................................................................... 3 Register 14 ................................................................................... 24 Supplemental Information for Mixers and IF DGAs .............. 5 Register 15 ................................................................................... 25 Timing Specifications .................................................................. 6 Applications Information .............................................................. 26 Absolute Maximum Ratings ............................................................ 7 Basic Connections ...................................................................... 26 ESD Caution .................................................................................. 7 Input Tuning ............................................................................... 26 Pin Configuration and Function Descriptions ............................. 8 Register Initialization Sequence ............................................... 26 Typical Performance Characteristics ........................................... 10 Standard Register Settings ......................................................... 27 Theory of Operation ...................................................................... 13 Readback ..................................................................................... 27 Dual Mixer Cores ....................................................................... 13 Daisy-Chain Mode ..................................................................... 28 DGA Basic Structure .................................................................. 13 IF Filter ........................................................................................ 30 Serial Input Shift Registers ........................................................ 14 Outline Dimensions ....................................................................... 31 Program Modes .......................................................................... 14 Ordering Guide .......................................................................... 31 Register Maps .................................................................................. 15 Register 0 Through Register 4 .................................................. 18 REVISION HISTORY 11/15Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Total Current, Low Power Mode Parameter, Table 1 ................................................................................................ 4 Change to Figure 4 ........................................................................... 8 Changes to Mixer A Enabled Section and Mixer B Enabled Section .............................................................................................. 23 Changes to Figure 51 Caption ...................................................... 31 1/15Revision 0: Initial Version Rev. A Page 2 of 31