400 MHz to 1250 MHz Quadrature Modulator with 750 MHz to 1150 MHz Frac-N PLL and Integrated VCO Data Sheet ADRF6701 modulator, PLL, and VCO provides for significant board FEATURES savings and reduces the BOM and design complexity. IQ modulator with integrated fractional-N PLL Output frequency range: 400 MHz to 1250 MHz The integrated fractional-N PLL/synthesizer generates a 2 f LO Internal LO frequency range: 750 MHz to 1150 MHz input to the IQ modulator. The phase detector together with an Output P1dB: 10.3 dBm 1100 MHz external loop filter is used to control the VCO output. The VCO Output IP3: 30.1 dBm 1100 MHz output is applied to a quadrature divider. To reduce spurious Noise floor: 159.4 dBm/Hz 1100 MHz components, a sigma-delta (-) modulator controls the Baseband bandwidth: 750 MHz (3 dB) programmable PLL divider. SPI serial interface for PLL programming The IQ modulator has wideband differential I and Q inputs, Integrated LDOs and LO buffer which support baseband as well as complex IF architectures. Power supply: 5 V/240 mA The single-ended modulator output is designed to drive a 50 40-lead 6 mm 6 mm LFCSP load impedance and can be disabled. APPLICATIONS The ADRF6701 is fabricated using an advanced silicon-germanium Cellular communications systems BiCMOS process. It is available in a 40-lead, exposed-paddle, Pb- GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE free, 6 mm 6 mm LFCSP package. Performance is specified from Broadband wireless access systems 40C to +85C. A lead-free evaluation board is available. Satellite modems Table 1. GENERAL DESCRIPTION IQ Modulator Part No. Internal LO Range 3 dB RF Output Range The ADRF6701 provides a quadrature modulator and ADRF6701 750 MHz 400 MHz synthesizer solution within a small 6 mm 6 mm footprint 1150 MHz 1250 MHz while requiring minimal external components. ADRF6702 1550 MHz 1200 MHz 2150 MHz 2400 MHz The ADRF6701 is designed for RF outputs from 400 MHz to ADRF6703 2100 MHz 1550 MHz 1250 MHz. The low phase noise VCO and high performance 2600 MHz 2650 MHz quadrature modulator make the ADRF6701 suitable for next ADRF6704 2500 MHz 2050 generation communication systems requiring high signal 290 MHz 3000 MHz dynamic range and linearity. The integration of the IQ FUNCTIONAL BLOCK DIAGRAM VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 34 29 27 22 17 10 1 36 LOSEL ADRF6701 40 LON 37 DECL3 DIVIDER BUFFER 2 9 DECL2 LOP 38 BUFFER 2 DECL1 DIVIDER 2:1 FRACTION INTEGER 2 12 MUX DATA MODULUS REG REG SPI CLK 13 INTERFACE LE 14 THIRD-ORDER FRACTIONAL 18 QP INTERPOLATOR VCO CORE 2 19 QN N COUNTER PRESCALER 2 21 TO 123 2 0/90 6 REFIN 32 IN MUX CHARGE PUMP 2 33 IP 250A, PHASE + FREQUENCY TEMP 500A (DEFAULT), 4 SENSOR DETECTOR 750A, 1000A MUXOUT 8 4 7 11 15 20 21 23 25 28 30 31 35 24 5 3 39 16 26 NC RSET CP VTUNE ENOP RFOUT GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20112012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08567-001ADRF6701 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Programming and Register Sequencing ..................... 19 Applications ....................................................................................... 1 Register Summary .......................................................................... 20 General Description ......................................................................... 1 Register Description ....................................................................... 21 Functional Block Diagram .............................................................. 1 Register 0Integer Divide Control (Default: 0x0001C0) .... 21 Revision History ............................................................................... 2 Register 1Modulus Divide Control (Default: 0x003001) .. 22 Specifications ..................................................................................... 3 Register 2Fractional Divide Control (Default: 0x001802) 22 Timing Characteristics ................................................................ 6 Register 3- Modulator Dither Control (Default: 0x10000B) .................................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Register 4PLL Charge Pump, PFD, and Reference Path ESD Caution .................................................................................. 7 Control (Default: 0x0AA7E4) ................................................... 24 Pin Configuration and Function Descriptions ............................. 8 Register 5LO Path and Modulator Control (Default: Typical Performance Characteristics ........................................... 10 0x0000D5) ................................................................................... 26 Theory of Operation ...................................................................... 16 Register 6VCO Control and VCO Enable (Default: PLL + VCO .................................................................................. 16 0x1E2106) .................................................................................... 27 Basic Connections for Operation ............................................. 16 Register 7External VCO Enable and Second lo divider .... 27 External LO ................................................................................. 16 Characterization Setups ................................................................. 28 Loop Filter ................................................................................... 17 Evaluation Board ............................................................................ 30 DAC-to-IQ Modulator Interfacing .......................................... 18 Evaluation Board Control Software ......................................... 30 Adding a Swing-Limiting Resistor ........................................... 18 Outline Dimensions ....................................................................... 35 IQ Filtering .................................................................................. 19 Ordering Guide .......................................................................... 35 Baseband Bandwidth ................................................................. 19 REVISION HISTORY 6/12Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 1 Changes to the Device Programming and Register Sequencing Section ........................................................................ 19 Changes to Figure 45 ...................................................................... 25 9/11Revision 0: Initial Version Rev. A Page 2 of 36