1550 MHz to 2650 MHz Quadrature Modulator with 2100 MHz to 2600 MHz Frac-N PLL and Integrated VCO Data Sheet ADRF6703 The integrated fractional-N PLL/synthesizer generates a 2 fLO FEATURES input to the IQ modulator. The phase detector together with an IQ modulator with integrated fractional-N PLL external loop filter is used to control the VCO output. The VCO RF output frequency range: 1550 MHz to 2650 MHz output is applied to a quadrature divider. To reduce spurious Internal LO frequency range: 2100 MHz to 2600 MHz components, a sigma-delta (-) modulator controls the Output P1dB: 14.2 dBm 2140 MHz programmable PLL divider. Output IP3: 33.2 dBm 2140 MHz Noise floor: 159.6 dBm/Hz 2140 MHz The IQ modulator has wideband differential I and Q inputs, Baseband bandwidth: 750 MHz (3 dB) which support baseband as well as complex IF architectures. SPI serial interface for PLL programming The single-ended modulator output is designed to drive a Integrated LDOs and LO buffer 50 load impedance and can be disa bled. Power supply: 5 V/240 mA The ADRF6703 is fabricated using an advanced silicon- 40-lead 6 mm 6 mm LFCSP germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, Pb-free, 6 mm 6 mm LFCSP package. APPLICATIONS Performance is specified from 40C to +85C. A lead-free Cellular communications systems evaluation board is available. GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE Broadband wireless access systems Table 1. Satellite modems Part No. Internal LO Range 3 dB RFOUT Balun Range ADRF6701 750 MHz 400 MHz GENERAL DESCRIPTION 1150 MHz 1250 MHz The ADRF6703 provides a quadrature modulator and ADRF6702 1550 MHz 1200 MHz synthesizer solution within a small 6 mm 6 mm footprint 2150 MHz 2400 MHz while requiring minimal external components. ADRF6703 2100 MHz 1550 MHz The ADRF6703 is designed for RF outputs from 1550 MHz to 2600 MHz 2650 MHz 2650 MHz. The low phase noise VCO and high performance ADRF6704 2500 MHz 2050 MHz quadrature modulator make the ADRF6703 suitable for next 290 MHz 3000 MHz generation communication systems requiring high signal dynamic range and linearity. The integration of the IQ modulator, PLL, and VCO provides for significant board savings and reduces the BOM and design complexity. FUNCTIONAL BLOCK DIAGRAM VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 34 29 27 22 17 10 1 ADRF6703 36 LOSEL 40 LON 37 DECL3 DIVIDER BUFFER 2 9 DECL2 LOP 38 2 BUFFER DECL1 2:1 FRACTION INTEGER MUX 12 DATA MODULUS REG REG SPI 13 CLK INTERFACE LE 14 THIRD-ORDER FRACTIONAL 18 QP INTERPOLATOR VCO CORE 2 N COUNTER 19 QN PRESCALER 2 21 TO 123 2 0/90 REFIN 6 32 IN MUX CHARGE PUMP 2 33 IP PHASE 250A, + TEMP FREQUENCY 500A (DEFAULT), 4 DETECTOR 750A, SENSOR 1000A 8 MUXOUT 4 7 11 15 20 21 23 25 28 30 31 35 24 33 39 16 26 5 NC RSET CP VTUNE ENOP RFOUT GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. 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Trademarks and registered trademarks are the property of their respective owners. 08570-001ADRF6703 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Programming and Register Sequencing ..................... 19 Applications ....................................................................................... 1 Register Summary .......................................................................... 20 General Description ......................................................................... 1 Register Description ....................................................................... 21 Functional Block Diagram .............................................................. 1 Register 0Integer Divide Control (Default: 0x0001C0) .... 21 Revision History ............................................................................... 2 Register 1Modulus Divide Control (Default: 0x003001) .. 22 Specifications ..................................................................................... 3 Register 2Fractional Divide Control (Default: 0x001802) 22 Timing Characteristics ................................................................ 6 Register 3- Modulator Dither Control (Default: 0x10000B) .................................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Register 4PLL Charge Pump, PFD, and Reference Path ESD Caution .................................................................................. 7 Control (Default: 0x0AA7E4) ................................................... 24 Pin Configuration and Function Descriptions ............................. 8 Register 5LO Path and Modulator Control (Default: Typical Performance Characteristics ........................................... 10 0x0000D5) ................................................................................... 26 Theory of Operation ...................................................................... 16 Register 6VCO Control and VCO Enable (Default: PLL + VCO .................................................................................. 16 0x1E2106) .................................................................................... 27 Basic Connections for Operation ............................................. 16 Register 7External VCO Enable ........................................... 27 External LO ................................................................................. 16 Characterization Setups ................................................................. 28 Loop Filter ................................................................................... 17 Evaluation Board ............................................................................ 30 DAC-to-IQ Modulator Interfacing .......................................... 18 Evaluation Board Control Software ......................................... 30 Adding a Swing-Limiting Resistor ........................................... 18 Outline Dimensions ....................................................................... 35 IQ Filtering .................................................................................. 19 Ordering Guide .......................................................................... 35 Baseband Bandwidth ................................................................. 19 REVISION HISTORY 10/11Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 6/11Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 5 ........................................................................ 10 Changes to Figure 17 and Figure 18 ............................................. 12 6/11Revision 0: Initial Version Rev. B Page 2 of 36