2050 MHz to 3000 MHz Quadrature Modulator with 2500 MHz to 2900 MHz Frac-N PLL and Integrated VCO Data Sheet ADRF6704 modulator, PLL, and VCO provides for significant board FEATURES savings and reduces the BOM and design complexity. IQ modulator with integrated fractional-N PLL Output frequency range: 2050 MHz to 3000 MHz The integrated fractional-N PLL/synthesizer generates a 2 f LO Internal LO frequency range: 2500 MHz to 2900 MHz input to the IQ modulator. The phase detector together with an Output P1dB: 12.1 dBm 2700 MHz external loop filter is used to control the VCO output. The VCO Output IP3: 27.2 dBm 2700 MHz output is applied to a quadrature divider. To reduce spurious Noise floor: 158.3 dBm/Hz 2700 MHz components, a sigma-delta (-) modulator controls the Baseband bandwidth: 750 MHz (3 dB) programmable PLL divider. SPI serial interface for PLL programming The IQ modulator has wideband differential I and Q inputs, Integrated LDOs and LO buffer which support baseband as well as complex IF architectures. Power supply: 5 V/226 mA The single-ended modulator output is designed to drive a 40-lead 6 mm 6 mm LFCSP 50 load impedance and can be disabled. APPLICATIONS The ADRF6704 is fabricated using an advanced silicon- Cellular communications systems germanium BiCMOS process. It is available in a 40-lead, GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE exposed-paddle, Pb-free, 6 mm 6 mm LFCSP package. Broadband wireless access systems Performance is specified from 40C to +85C. A lead-free Satellite modems evaluation board is available. GENERAL DESCRIPTION Table 1. IQ Modulator The ADRF6704 provides a quadrature modulator and Part No. Internal LO Range 3 dB RF Output Range synthesizer solution within a small 6 mm 6 mm footprint ADRF6701 750 MHz 400 MHz while requiring minimal external components. 1150 MHz 1250 MHz The ADRF6704 is designed for RF outputs from 2050 MHz to ADRF6702 1550 MHz 1200 MHz 3000 MHz. The low phase noise VCO and high performance 2150 MHz 2400 MHz quadrature modulator make the ADRF6704 suitable for next ADRF6703 2100 MHz 1550 MHz generation communication systems requiring high signal 2600 MHz 2650 MHz dynamic range and linearity. The integration of the IQ ADRF6704 2500 MHz 2050 MHz 2900 MHz 3000 MHz FUNCTIONAL BLOCK DIAGRAM VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 34 29 27 22 17 10 1 36 LOSEL ADRF6704 40 LON 37 DECL3 DIVIDER BUFFER 2 9 DECL2 38 LOP BUFFER 2 DECL1 2:1 FRACTION INTEGER MUX 12 DATA MODULUS REG REG SPI CLK 13 INTERFACE 14 LE THIRD-ORDER FRACTIONAL 18 QP INTERPOLATOR VCO CORE 19 2 N COUNTER QN PRESCALER 2 21 TO 123 2 0/90 REFIN 6 32 IN MUX CHARGE PUMP 2 33 IP PHASE 250A, + FREQUENCY 500A (DEFAULT), TEMP 4 DETECTOR SENSOR 750A, 1000A MUXOUT 8 4 7 11 15 20 21 23 25 28 30 31 35 24 5 3 39 16 26 NC RSET CP VTUNE ENOP RFOUT GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 08571-001ADRF6704 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Baseband Bandwidth ................................................................. 19 Applications....................................................................................... 1 Device Programming and Register Sequencing..................... 19 General Description ......................................................................... 1 Register Summary .......................................................................... 20 Functional Block Diagram .............................................................. 1 Register Description....................................................................... 21 Revision History ............................................................................... 2 Register 0Integer Divide Control (Default: 0x0001C0) .... 21 Specifications..................................................................................... 3 Register 1Modulus Divide Control (Default: 0x003001).. 22 Timing Characteristics ................................................................ 6 Register 2Fractional Divide Control (Default: 0x001802)..22 Absolute Maximum Ratings............................................................ 7 Register 3- Modulator Dither Control (Default: 0x10000B).................................................................................... 23 ESD Caution.................................................................................. 7 Register 4PLL Charge Pump, PFD, and Reference Path Pin Configuration and Function Descriptions............................. 8 Control (Default: 0x12A7E4).................................................... 24 Typical Performance Characteristics ........................................... 10 Register 5LO Path and Modulator Control (Default: Theory of Operation ...................................................................... 16 0x0000E5).................................................................................... 26 PLL + VCO.................................................................................. 16 Register 6VCO Control and VCO Enable (Default: Basic Connections for Operation............................................. 16 0x1E2106).................................................................................... 27 External LO ................................................................................. 16 Characterization Setups................................................................. 28 Loop Filter ................................................................................... 17 Evaluation Board ............................................................................ 30 DAC-to-IQ Modulator Interfacing .......................................... 18 Evaluation Board Control Software......................................... 30 Adding a Swing-Limiting Resistor........................................... 18 Outline Dimensions....................................................................... 35 IQ Filtering.................................................................................. 19 Ordering Guide .......................................................................... 35 REVISION HISTORY 10/11Revision 0: Initial Version Rev. 0 Page 2 of 36