750 MHz to 1150 MHz Quadrature Demodulator with Fractional-N PLL and VCO Data Sheet ADRF6801 FEATURES GENERAL DESCRIPTION IQ demodulator with integrated fractional-N PLL The ADRF6801 is a high dynamic range IQ demodulator with LO frequency range: 750 MHz to 1150 MHz integrated PLL and VCO. The fractional-N PLL/synthesizer Input P1dB: 12.5 dBm generates a frequency in the range of 3.0 GHz to 4.6 GHz. A Input IP3: 25 dBm divide-by-4 quadrature divider divides the output frequency of Noise figure (DSB): 14.3 dB the VCO down to the required local oscillator (LO) frequency Voltage conversion gain: 5.1 dB to drive the mixers in quadrature. Additionally, an output buffer Quadrature demodulation accuracy can be enabled that generates an f /2 signal for external use. VCO Phase accuracy: 0.3 The PLL reference input is supported from 10 MHz to 160 MHz. Amplitude accuracy: 0.05 dB The phase detector output controls a charge pump whose output Baseband demodulation: 275 MHz, 3 dB bandwidth is integrated in an off-chip loop filter. The loop filter output is SPI serial interface for PLL programming then applied to an integrated VCO. 40-lead, 6 mm 6 mm LFCSP The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential APPLICATIONS I and Q output paths have excellent quadrature accuracy and QAM/QPSK RF/IF demodulators can handle baseband signaling or complex IF up to 120 MHz. Cellular W-CDMA/CDMA/CDMA2000 The ADRF6801 is fabricated using an advanced silicon-germanium Microwave point-to-(multi)point radios BiCMOS process. It is available in a 40-lead, exposed-paddle, Broadband wireless and WiMAX RoHS-compliant, 6 mm 6 mm LFCSP package. Performance is specified over the 40C to +85C temperature range. FUNCTIONAL BLOCK DIAGRAM GND VCCLO VCCLO LOSEL IBBP IBBN GND 35 34 36 33 32 31 17 BUFFER 30 ADRF6801 GND CTRL LON 37 29 VCCBB BUFFER 28 GND 38 LOP 27 VCCRF DIVIDER BUFFER FRACTION INTEGER 1 MODULUS 11 MUX GND REG REG OR 2 12 DATA SPI THIRD-ORDER QUAD CLK 13 INTERFACE 26 RFIN FRACTIONAL 2 LE 14 INTERPOLATOR PRESCALER 15 VCO GND N COUNTER 25 GNDRF 2 CORE 2 24 GND REFIN 6 PHASE MUX + TEMP 23 GND FREQUENCY CHARGE PUMP 2 SENSOR DETECTOR 250A, 7 GND 22 500A (DEFAULT), VCCBB 4 750A, 3.3V LDO 2.5V LDO VCO LDO 1000A 21 GND MUXOUT 8 3 4 5 9 39 40 18 19 20 1 2 10 16 VCC1 DECL3 VCC2 GND CPOUT GND RSET DECL2 VTUNE DECL1 QBBP QBBN GND Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. 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Technical Support www.analog.com 09576-001ADRF6801 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Structure ....................................................................... 14 Applications ....................................................................................... 1 Applications Information .............................................................. 21 General Description ......................................................................... 1 Basic Connections ...................................................................... 21 Functional Block Diagram .............................................................. 1 Supply Connections ................................................................... 21 Revision History ............................................................................... 2 Synthesizer Connections ........................................................... 21 Specifications ..................................................................................... 3 I/Q Output Connections ........................................................... 22 Timing Characteristics ................................................................ 5 RF Input Connections ............................................................... 22 Absolute Maximum Ratings ............................................................ 6 Charge Pump/VTUNE Connections ...................................... 22 Pin Configuration and Function Descriptions ............................. 7 LO Select Interface ..................................................................... 22 Typical Performance Characteristics ............................................. 9 External LO Interface ................................................................ 22 Synthesizer/PLL .......................................................................... 12 Setting the Frequency of the PLL ............................................. 22 Complementary Cumulative Distribution Functions (CCDF) Register Programming ............................................................... 22 ....................................................................................................... 13 EVM Measurements .................................................................. 23 Circuit Description ......................................................................... 14 Evaluation Board Layout and Thermal Grounding ................... 24 LO Quadrature Drive ................................................................. 14 ADRF6801 Software .................................................................. 28 V-to-I Converter ......................................................................... 14 Characterization Setups ................................................................. 30 Mixers........................................................................................... 14 Outline Dimensions ....................................................................... 34 Emitter Follower Buffers ........................................................... 14 Ordering Guide .......................................................................... 34 Bias Circuitry .............................................................................. 14 REVISION HISTORY 6/2018Rev. 0 to Rev. A Change to Register Structure Section .......................................... 14 Changes to Register Programming Section ................................ 22 1/2011Revision 0: Initial Version Rev. A Page 2 of 34