X-On Electronics has gained recognition as a prominent supplier of ADRF6807ACPZ-R7 Modulator/Demodulator across the USA, India, Europe, Australia, and various other global locations. ADRF6807ACPZ-R7 Modulator/Demodulator are a product manufactured by Analog Devices. We provide cost-effective solutions for Modulator/Demodulator, ensuring timely deliveries around the world.

ADRF6807ACPZ-R7 Analog Devices

ADRF6807ACPZ-R7 electronic component of Analog Devices
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Part No.ADRF6807ACPZ-R7
Manufacturer: Analog Devices
Category: Modulator/Demodulator
Description: RF Demodulator IC 700MHz ~ 1.05GHz 40-VFQFN Exposed Pad, CSP
Datasheet: ADRF6807ACPZ-R7 Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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We are delighted to provide the ADRF6807ACPZ-R7 from our Modulator/Demodulator category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the ADRF6807ACPZ-R7 and other electronic components in the Modulator/Demodulator category and beyond.

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700 MHz to 1050 MHz Quadrature Demodulator with Fractional-N PLL Data Sheet ADRF6807 FEATURES GENERAL DESCRIPTION IQ demodulator with integrated fractional-N PLL The ADRF6807 is a high dynamic range IQ demodulator with LO frequency range: 700 MHz to 1050 MHz integrated phase-locked loop (PLL) and voltage controlled For the following specifications (LPEN = 0)/(LPEN = 1): oscillator (VCO). The fractional-N PLL/synthesizer generates a Input P1dB: 12.8 dBm/11.7 dBm frequency in the range of 2.8 GHz to 4.2 GHz. A programmable Input IP3: 26.7 dBm/24.0 dBm quadrature divider (divide ratio = 4) divides the output frequency Noise figure (DSB): 13.1 dB/12.4 dB of the VCO down to the required local oscillator (LO) frequency to Voltage conversion gain: 1.0 dB/4.3 dB drive the mixers in quadrature. Additionally, an output divider Quadrature demodulation accuracy (divide ratio = 4 to 8) generates a divided-down VCO signal for Phase accuracy: <0.5 external use. Amplitude accuracy: <0.1 dB The PLL reference input is supported from 9 MHz to 160 MHz. Baseband demodulation: 170 MHz/135 MHz, 3 dB The phase detector output controls a charge pump whose output bandwidth is integrated in an off-chip loop filter. The loop filter output is SPI serial interface for PLL programming then applied to an integrated VCO. 40-lead, 6 mm 6 mm LFCSP The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential APPLICATIONS I and Q output paths have excellent quadrature accuracy and QAM/QPSK RF/IF demodulators can handle baseband signaling or complex IF up to 120 MHz. Cellular W-CDMA/CDMA/CDMA2000 A reduced power mode of operation is also provided by Microwave point-to-(multi)point radios programming the serial interface registers to reduce current Broadband wireless and WiMAX consumption, with slightly degraded input linearity and output current drive. The ADRF6807 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed paddle, RoHS-compliant, 6 mm 6 mm LFCSP package. Performance is specified over the 40C to +85C temperature range. FUNCTIONAL BLOCK DIAGRAM VCCLO GND VCCLO LOSEL IBBP IBBN GND 35 34 36 33 32 31 17 BUFFER 30 GND CTRL ADRF6807 DIV LON 37 29 DECL3 4, BUFFER 6, 28 VCCRF LOP 38 8 27 GND BUFFER INTEGER FRACTION DIVIDER MODULUS GND 11 MUX REG REG 2 DATA 12 SPI 26 RFIN THIRD-ORDER QUAD CLK 13 INTERFACE FRACTIONAL 2 25 14 RFIP LE INTERPOLATOR PRESCALER VCO 15 GND N COUNTER 2 CORE 2 24 GND 6 REFIN PHASE MUX + 23 CHARGE PUMP VOCM FREQUENCY 2 TEMP DETECTOR 250A, GND 7 SENSOR 22 500A (DEFAULT), VCCBB 4 750A, 2.5V LDO VCO LDO 1000A 21 GND MUXOUT 8 1 2 3 4 5 9 10 39 40 18 19 20 16 VCC1 VCC1 CPOUT GND RSET DECL2 VCC2 VTUNE DECL1 GND QBBP QBBN GND Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 20112012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 09993-001ADRF6807 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Register Structure....................................................................... 14 Applications....................................................................................... 1 LO Divider Programming......................................................... 21 General Description ......................................................................... 1 Programming Example.............................................................. 21 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 22 Revision History ............................................................................... 2 Basic Connections...................................................................... 22 Specifications..................................................................................... 3 Supply Connections ................................................................... 22 Timing Characteristics ................................................................ 5 Synthesizer Connections........................................................... 22 Absolute Maximum Ratings............................................................ 6 I/Q Output Connections ........................................................... 23 ESD Caution.................................................................................. 6 RF Input Connections ............................................................... 23 Pin Configuration and Function Descriptions............................. 7 Charge Pump/VTUNE Connections ...................................... 23 Typical Performance Characteristics ............................................. 9 LO Select Interface ..................................................................... 23 Synthesizer/PLL.......................................................................... 12 External LO Interface ................................................................ 23 Complementary Cumulative Distribution Functions Setting the Frequency of the PLL............................................. 23 (CCDF) ........................................................................................ 13 Register Programming............................................................... 23 Circuit Description......................................................................... 14 EVM Measurements .................................................................. 24 LO Quadrature Drive................................................................. 14 Evaluation Board Layout and Thermal Grounding................... 25 V-to-I Converter......................................................................... 14 ADRF6807 Software .................................................................. 30 Mixers .......................................................................................... 14 Characterization Setups................................................................. 32 Emitter Follower Buffers ........................................................... 14 Outline Dimensions....................................................................... 36 Bias Circuitry .............................................................................. 14 Ordering Guide .......................................................................... 36 REVISION HISTORY 2/12Rev. A to Rev. B Changes to Table 1............................................................................ 3 Changes to Figure 21 and to Changes to Figure 24 Through Figure 26 .......................................................................................... 12 Changes to Figure 34...................................................................... 16 Changes to Figure 37...................................................................... 18 Changes to Figure 38...................................................................... 19 Changes to Figure 39...................................................................... 20 Changes to EVM Measurements Section and Changes to Figure 42 .......................................................................................... 24 Changes to Figure 43...................................................................... 25 Added Figure 44 Renumbered Sequentially .............................. 26 Changes to Figure 45 and Figure 46............................................. 27 Changes to Table 7.......................................................................... 29 Changes to Figure 47...................................................................... 30 Changes to Figure 48...................................................................... 31 9/11Rev. 0 to Rev. A Changes to EVM Measurements Section and Figure 42........... 24 8/11Revision 0: Initial Version Rev. B Page 2 of 36

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