695 MHz to 2700 MHz, Quadrature Demodulator with Integrated Fractional-N PLL and VCO Data Sheet ADRF6820 FEATURES FUNCTIONAL BLOCK DIAGRAM I/Q demodulator with integrated fractional-N PLL RF input frequency range: 695 MHz to 2700 MHz 15 14 13 24 2 3 8 9 23 25 26 28 38 Internal LO frequency range: 356.25 MHz to 2850 MHz 4 I+ DC/PHASE SERIAL PORT Input P1dB: 14.5 dBm at 1900 MHz RF CORRECTION 5 I INTERFACE Input IP3: 35 dBm at 1900 MHz RF POLYPHASE 29 RFIN0 FILTER Programmable HD3/IP3 trim 35 LOIN+ Single pole, double throw (SPDT) RF input switch RFIN1 22 34 LOIN QUAD RF digital step attenuation range: 0 dB to 15 dB DIVIDER PLL 39 REFIN Integrated RF tunable balun for single-ended 50 input Multicore integrated VCO 6 Q LDO LDO DC/PHASE Demodulated 1 dB bandwidth: 600 MHz 2.5V VCO CORRECTION 7 Q+ Demodulated 3 dB bandwidth: 1400 MHz 1 19 30 31 36 10 27 33 40 11 21 4 selectable baseband gain and bandwidth modes VPOS 5V DECL1 TO VPOS 3P3 DECL4 Digital programmable LO phase offset and dc nulling Figure 1. Programmable via 3-wire serial port interface (SPI) 40-lead, 6 mm 6 mm LFCSP APPLICATIONS Cellular W-CDMA/GSM/LTE Digital predistortion (DPD) receivers Microwave point-to-point radios GENERAL DESCRIPTION The ADRF6820 is a highly integrated demodulator and synthesizer on-chip fractional-N synthesizer. The integrated synthesizer ideally suited for next generation communication systems. The enables continuous LO coverage from 356.25 MHz to 2850 MHz. feature rich device consists of a high linearity broadband I/Q The PLL reference input can support a wide frequency range demodulator, an integrated fractional-N phase-locked loop (PLL), because the divide or multiplication blocks can increase or and a low phase noise multicore, voltage controlled oscillator decrease the reference frequency to the desired value before it (VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip is passed to the phase frequency detector (PFD). tunable RF balun, a programmable RF attenuator, and two low When selected, the output of the internal fractional-N synthesizer dropout (LDO) regulators. This highly integrated device fits is applied to a divide-by-2 quadrature phase splitter. From the within a small 6 mm 6 mm footprint. external LO path, a 1 LO signal can be applied to the built-in The high isolation 2:1 RF switch and on-chip tunable RF balun polyphase filter, or a 2 LO signal can be used with the divide- by-2 quadrature phase splitter to generate the quadrature LO enable the ADRF6820 to support two single-ended, 50 terminated RF inputs. A programmable attenuator ensures inputs to the mixers. an optimal differential RF input level to the high linearity The ADRF6820 is fabricated using an advanced silicon-germanium demodulator core. The integrated attenuator offers an BiCMOS process. It is available in a 40-lead, RoHS-compliant, attenuation range of 0 dB to 15 dB with a step size of 1 dB. 6 mm 6 mm LFCSP package with an exposed paddle. The ADRF6820 offers two alternatives for generating the Performance is specified over the 40C to +85C temperature differential local oscillator (LO) input signal: externally via a range. high frequency, low phase noise LO signal or internally via the Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20132016 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com CS SCLK SDIO ENBL 11990-001ADRF6820 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LO Generation Block ................................................................. 15 Applications ....................................................................................... 1 Active Mixers .............................................................................. 17 Functional Block Diagram .............................................................. 1 Baseband Buffers ........................................................................ 17 General Description ......................................................................... 1 Serial Port Interface (SPI) ......................................................... 17 Revision History ............................................................................... 2 Power Supply Sequencing ......................................................... 17 Specifications ..................................................................................... 3 Applications Information .............................................................. 18 System Specifications ................................................................... 3 Basic Connections ...................................................................... 18 Dynamic Performance ................................................................. 3 RF Balun Insertion Loss Optimization ................................... 20 Synthesizer/PLL Specifications ................................................... 5 Bandwidth Select Modes ........................................................... 21 Digital Logic Specifications ......................................................... 6 IP3 and Noise Figure Optimization ......................................... 23 Absolute Maximum Ratings ............................................................ 7 I/Q Output Loading ................................................................... 26 Thermal Resistance ...................................................................... 7 Image Rejection .......................................................................... 27 ESD Caution .................................................................................. 7 I/Q Polarity .................................................................................. 28 Pin Configuration and Function Descriptions ............................. 8 Layout .......................................................................................... 29 Typical Performance Characteristics ............................................. 9 Register Map ................................................................................... 30 Theory of Operation ...................................................................... 14 Register Address Descriptions .................................................. 31 RF Input Switch .......................................................................... 14 Outline Dimensions ....................................................................... 45 Tunable Balun ............................................................................. 14 Ordering Guide .......................................................................... 45 RF Attenuator .............................................................................. 15 REVISION HISTORY 8/2016Rev. B to Rev. C 3/2014Rev. 0 to Rev. A Changes to Figure 3 .......................................................................... 8 Changes to Features Section ............................................................ 1 Updated Outline Dimensions ....................................................... 45 Added LO Harmonic Rejection Parameter and DSA Attenuation Accuracy Parameter, Table 1 ............................................................ 3 4/2015Rev. A to Rev. B Changes to Table 2 ............................................................................. 3 Changes to Features Section and Figure 1..................................... 1 Changes to Table 3 ............................................................................. 5 Changes to Table 1 ............................................................................ 3 Changes to Figure 5 and Figure 8 .................................................... 9 Changes to Figure 3 .......................................................................... 8 Changes to Figure 21 and Figure 22 ............................................ 12 Changes to Figure 15 and Figure 16 ............................................. 11 Changes to Table 17 ....................................................................... 30 Changes to Figure 25 ...................................................................... 12 Added Address: 0x44, Reset: 0x0000, Name: DIV SM CTL Added Power Supply Sequencing Section ................................... 17 Section and Table 36 Renumbered Sequentially ....................... 43 Changes to Figure 33 and Table 14 ............................................... 18 Changes to Address: 0x45, Reset: 0x0000, Name: VCO CTL2 Changes to Figure 38 ...................................................................... 21 Section and Table 37 ...................................................................... 44 Added Address: 0x46, Reset: 0x0000, Name: VCO RB Section Changes to Figure 51 ...................................................................... 27 Changes to Address: 0x00, Reset: 0x0000, Name: SOFT RESET and Table 38 .................................................................................... 44 Section .............................................................................................. 31 Changes to Address: 0x33, Reset: 0x0000, Name: MOD CTL1 12/2013Revision 0: Initial Version Section and Table 31 ....................................................................... 40 Rev. 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