450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO Data Sheet ADRF6821 The high isolation 2:1 RF switch and on-chip wideband RF FEATURES balun enable the ADRF6821 to support two single-ended, 50 DPD receiver with integrated fractional-N PLL terminated RF inputs. A programmable attenuator ensures an RF input frequency range: 450 MHz to 2800 MHz optimal differential RF input level to the high linearity demodulator Internal LO input frequency range: 450 MHz to 2800 MHz core. The integrated attenuator offers an attenuation range of Dual RF inputs with SPDT absorptive RF switches 15 dB with a step size of 1 dB. High linearity IF amplifiers follow Integrated RF balun for single-ended 50 input the demodulator and provide an interface to the next component Integrated VCO to cover complete RF input range in the chain, typically an analog-to-digital converter (ADC). Digital programmable LO phase offset and dc nulling Programmable via 4-wire SPI The ADRF6821 offers two alternatives for generating the 56-lead, 8 mm 8 mm LFCSP differential local oscillator (LO) input signal: internally via the on-chip fractional-N synthesizer with low phase noise APPLICATIONS VCOs or externally via a low phase noise LO signal. The Cellular W-CDMA/GSM/LTE integrated synthesizer enables continuous LO coverage from DPD receivers 450 MHz to 2800 MHz. The PLL reference input supports a Microwave, point to point radios wide frequency range and includes integrated reference dividers before the phase frequency detector (PFD). GENERAL DESCRIPTION When selected, the output of the internal fractional-N synthesizer The ADRF6821 is a highly integrated, dual radio frequency (RF) is applied to a divide by 2, quadrature phase splitter. From the input, zero intermediate frequency (IF)/low IF RFIC receiver external LO path, a 2 LO signal can be used with the divide by 2, with a quadrature demodulator, digital step attenuator (DSA), quadrature phase splitter to generate the quadrature LO inputs IF linear amplifiers, an integrated, fractional-N phase-locked loop to the mixers. (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication The ADRF6821 is fabricated using an advanced silicon germanium digital predistortion (DPD) systems. (SiGe), bipolar complementary metal oxide semiconductor (BiCMOS) process. It is available in a 56-lead, RoHS compliant, 8 mm 8 mm LFCSP package with an exposed pad. Performance is specified over the 40C to +105C case temperature range. FUNCTIONAL BLOCK DIAGRAM IF QOUT+ IF QOUT 54 53 DC DAC /R RFIN FB0 4 PFD 41 CPOUT CP - /N RF SEL0 9 0 30 VTUNE RF SEL1 10 2 90 32 EX LO IN 31 EX LO IN+ 39 LO OUT 38 LO OUT+ RFIN FB1 11 SPI DC DAC 17 18 24 25 26 27 IF IOUT+ IF IOUT SCLK SDIO SDO CS Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20172018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 14807-001ADRF6821 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RF Attenuator ............................................................................. 21 Applications ....................................................................................... 1 Active Mixer ................................................................................ 21 General Description ......................................................................... 1 I and Q Polarity .......................................................................... 21 Functional Block Diagram .............................................................. 1 Low-Pass Filters (LPF) and IF Amplifiers ............................... 21 Revision History ............................................................................... 2 LO Generation Block ................................................................. 21 Specifications ..................................................................................... 3 Register Write Sequence ............................................................ 24 System Specifications ................................................................... 4 Serial Peripheral Interface (SPI) ............................................... 24 DSA and RF Input Switch Specifications .................................. 5 Applications Information .............................................................. 25 PLL/VCO Specifications .............................................................. 6 Basic Connections ...................................................................... 25 Digital Logic Specifications ......................................................... 7 Low-Pass Filter Bandwidth Selection ...................................... 28 Serial Peripheral Interface (SPI) Timing Specifications .......... 8 I/Q Output Loading ................................................................... 29 Absolute Maximum Ratings ............................................................ 9 Analog-to-Digital Converter (ADC) Interfacing ................... 29 Thermal Resistance ...................................................................... 9 Image Rejection .......................................................................... 31 ESD Caution .................................................................................. 9 Power Supply Configuration..................................................... 32 Pin Configuration and Function Descriptions ........................... 10 Layout .......................................................................................... 34 Typical Performance Characteristics ........................................... 12 Register Map and Register Descriptions ..................................... 35 Phase-Locked Loop (PLL) Performance ................................. 17 Register Descriptions ................................................................. 38 Theory of Operation ...................................................................... 20 Outline Dimensions ....................................................................... 61 RF Input Switch .......................................................................... 20 Ordering Guide .......................................................................... 61 Balun ............................................................................................ 21 REVISION HISTORY 8/2018Rev. 0 to Rev. A Changed VCC AMP I Pin and VCC MIX I Pin to VCC IFMIX I Pin ........................................................ Throughout Changed VCC MIX Q Pin and VCC AMP Q Pin to VCC IFMIX Q Pin ..................................................... Throughout Changes to Figure 3 ........................................................................ 10 Changes to Figure 62 ...................................................................... 32 Updated Outline Dimensions ....................................................... 62 5/2017Revision 0: Initial Version Rev. A Page 2 of 61