Integrated Dual RF Transmitters and Observation Receiver Data Sheet ADRV9008-2 global system for mobile communications (MC GSM) mode, FEATURES which has higher inband spurious-free dynamic range (SFDR), Dual transmitters the maximum large signal bandwidth is 75 MHz. Dual input shared observation receiver Maximum tunable transmitter synthesis bandwidth: 450 MHz The observation path consists of a wide bandwidth direct Maximum observation receiver bandwidth: 450 MHz conversion receiver with state of the art dynamic range. The Fully integrated fractional-N RF synthesizers complete receive subsystem includes dc offset correction, Fully integrated clock synthesizer quadrature correction, and digital filtering, thus eliminating the Multichip phase synchronization for RF LO and baseband need for these functions in the digital baseband. Several clocks auxiliary functions such as analog-to-digital converters (ADCs), JESD204B datapath interface digital-to-analog converters (DACs), and general-purpose Tuning range (center frequency): 75 MHz to 6000 MHz inputs/outputs (GPIOs) for power amplifier (PA) and radio frequency (RF) front-end control are also integrated. APPLICATIONS 2G/3G/4G/5G macrocell base stations The fully integrated phase-locked loops (PLLs) provide high Active antenna systems performance, low power fractional-N RF frequency synthesis for Massive multiple input, multiple output (MIMO) the transmitter and receiver sections. An additional synthesizer Phased array radars generates the clocks needed for the converters, digital circuits, and Electronic warfare the serial interface. Special precautions have been taken to Military communications provide the isolation required in high performance base station Portable test equipment applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated. GENERAL DESCRIPTION The high speed JESD204B interface supports up to 12.288 Gbps The ADRV9008-2 is a highly integrated, RF agile transmit lane rates, resulting in two lanes per transmitter in the widest subsystem offering dual-channel transmitters, an observation path bandwidth mode and two lanes for the observation path receiver, integrated synthesizers, and digital signal processing receiver in the widest bandwidth mode. functions. The IC delivers a versatile combination of high performance and low power consumption required by The core of the ADRV9008-2 can be powered directly from 2G/3G/4G/5G macrocell base stations, and active antenna 1.3 V regulators and 1.8 V regulators and is controlled via a applications. standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The transmitters use an innovative direct conversion modulator The ADRV9008-2 is packaged in a 12 mm 12 mm 196-ball that achieves multicarrier macrocell base station quality chip scale ball grid array (CSP BGA). performance and low power. In 3G/4G mode, the maximum transmitter large signal bandwidth is 200 MHz. In multicarrier Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2018 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com ADRV9008-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 69 Applications ....................................................................................... 1 Transmitter .................................................................................. 69 General Description ......................................................................... 1 Observation Receiver ................................................................. 69 Revision History ............................................................................... 2 Clock Input .................................................................................. 69 Functional Block Diagram .............................................................. 3 Synthesizers ................................................................................. 69 Specifications ..................................................................................... 4 Serial Peripheral Interface (SPI) ............................................... 69 Current and Power Consumption Specifications ................... 13 JTAG Boundary Scan ................................................................. 69 Timing Diagrams ........................................................................ 14 Power Supply Sequence ............................................................. 69 Absolute Maximum Ratings .......................................................... 15 GPIO x Pins ............................................................................... 70 Reflow Profile .............................................................................. 15 Auxiliary Converters .................................................................. 70 Thermal Management ............................................................... 15 JESD204B Data Interface .......................................................... 70 Thermal Resistance .................................................................... 15 Applications Information .............................................................. 71 ESD Caution ................................................................................ 15 PCB Layout and Power Supply Recommendations ............... 71 Pin Configuration and Function Descriptions ........................... 16 PCB Material and Stackup Selection ....................................... 71 Typical Performance Characteristics ........................................... 23 Fanout and Trace Space Guidelines ......................................... 73 75 MHz to 525 MHz Band ........................................................ 23 Component Placement and Routing Guidelines ................... 74 650 MHz to 3000 MHz Band .................................................... 36 RF and JESD204B Transmission Line Layout ........................ 79 3400 MHz to 4800 MHz Band .................................................. 47 Isolation Techniques Used on the ADRV9008-2W/PCBZ ... 83 5100 MHz to 5900 MHz Band .................................................. 57 RF Port Interface Information .................................................. 85 Transmitter Output Impedance ................................................ 67 Outline Dimensions ....................................................................... 95 Observation Receiver Input Impedance .................................. 67 Ordering Guide .......................................................................... 95 Terminology .................................................................................... 68 REVISION HISTORY 9/2018Revision 0: Initial Version Rev. 0 Page 2 of 95