Integrated, Dual RF Transceiver with Observation Path Data Sheet AD9375 The transceiver consists of wideband direct conversion signal FEATURES paths with state-of-the-art noise figure and linearity. Each complete Dual differential Tx Rx and Tx subsystem includes dc offset correction, quadrature error Dual differential Rx correction (QEC), and programmable digital filters, eliminating Observation receiver with 2 inputs the need for these functions in the digital baseband. Several Fully integrated, ultralow power DPD actuator and adaptation auxiliary functions such as an auxiliary analog-to-digital converter engine for PA linearization Sniffer receiver with 3 inputs (ADC), auxiliary digital-to-analog converters (DACs), and general- Tunable range: 300 MHz to 6000 MHz purpose input/outputs (GPIOs) are integrated to provide additional Linearization signal BW to 40 MHz monitoring and control capability. Tx synthesis BW to 250 MHz An ORx channel with two inputs is included to monitor each Tx Rx BW: 8 MHz to 100 MHz output and implement calibration applications. This channel also Supports FDD and TDD operation connects to three sniffer receiver (SnRx) inputs that can monitor Fully integrated independent fractional-N RF synthesizers for radio activity in different bands. Tx, Rx, ORx, and clock generation The high speed JESD204B interface supports lane rates up to JESD204B digital interface 6144 Mbps. Four lanes are dedicated to the transmitters and four APPLICATIONS lanes are dedicated to the receiver and observation receiver channels. 3G/4G small cell base transceiver station (BTS) The fully integrated phase-locked loops (PLLs) provide high 3G/4G massive MIMO/active antenna systems performance, low power, fractional-N frequency synthesis for GENERAL DESCRIPTION the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high The AD9375 is a highly integrated, wideband radio frequency (RF) performance base station applications. All voltage controlled transceiver offering dual-channel transmitters (Tx) and receivers oscillator (VCO) and loop filter components are integrated to (Rx), integrated synthesizers, a fully integrated digital predistortion minimize the external component count. (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high The device contains a fully integrated, low power DPD actuator performance and low power consumption required by 3G/4G and adaptation engine for use in PA linearization. The DPD feature small cell and massive multiple input, multiple output (MIMO) enables use of high efficiency PAs, significantly reducing the power equipment in both frequency division duplex (FDD) and time consumption of small cell base station radios while also reducing division duplex (TDD) applications. The AD9375 operates from the number of JESD204B lanes necessary to interface with baseband 300 MHz to 6000 MHz, covering most of the licensed and unlicensed processors. cellular bands. The DPD algorithm supports linearization on A 1.3 V supply is required to power the AD9375 core, and a signal bandwidths up to 40 MHz depending on the power amplifier standard 4-wire serial port controls it. Other voltage supplies (PA) characteristics (for example, two adjacent 20 MHz carriers). provide proper digital interface levels and optimize transmitter The IC supports Rx bandwidths up to 100 MHz. It also supports and auxiliary converter performance. The AD9375 is packaged in a observation receiver (ORx) and Tx synthesis bandwidths up to 12 mm 12 mm, 196-ball chip scale ball grid array (CSP BGA). 250 MHz to accommodate digital correction algorithms. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 2017 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com AD9375 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 56 Applications ....................................................................................... 1 Transmitter (Tx) ......................................................................... 56 General Description ......................................................................... 1 Receiver (Rx) ............................................................................... 56 Revision History ............................................................................... 2 Observation Receiver (ORx) ..................................................... 56 Functional Block Diagram .............................................................. 3 Sniffer Receiver (SnRx) ............................................................. 56 Specifications ..................................................................................... 4 Clock Input.................................................................................. 56 Current and Power Consumption Specifications................... 10 Synthesizers ................................................................................. 57 Timing Specifications ................................................................ 12 Serial Peripheral Interface (SPI) ............................................... 57 Absolute Maximum Ratings .......................................................... 14 GPIO x AND GPIO 3P3 x Pins ............................................ 57 Reflow Profile .............................................................................. 14 Auxiliary Converters .................................................................. 57 Thermal Resistance .................................................................... 14 JESD204B Data Interface .......................................................... 58 ESD Caution ................................................................................ 14 Power Supply Sequence ............................................................. 58 Pin Configuration and Function Descriptions ........................... 15 Digital Predistortion (DPD) ..................................................... 59 Typical Performance Characteristics ........................................... 18 JTAG Boundary Scan ................................................................. 60 700 MHz Band ............................................................................ 18 Outline Dimensions ....................................................................... 61 2.6 GHz Band .............................................................................. 28 Ordering Guide .......................................................................... 61 3.5 GHz Band .............................................................................. 38 5.5 GHz Band .............................................................................. 48 REVISION HISTORY 3/2017Revision 0: Initial Version Rev. 0 Page 2 of 61