Commercial Grade SHARC DSP Microcomputer a ADSP-21061/ADSP-21061L Dual data address generators with modulo and bit-reverse SUMMARY addressing High performance signal processor for communications, Efficient program sequencing with zero-overhead looping: graphics, and imaging applications single-cycle loop setup Super Harvard Architecture IEEE JTAG Standard 1149.1 test access port and on-chip Four independent buses for dual data fetch, instruction emulation fetch, and nonintrusive I/O 32-bit single-precision and 40-bit extended-precision IEEE 32-bit IEEE floating-point computation unitsmultiplier, floating-point data formats or 32-bit fixed-point data ALU, and shifter format Dual-ported on-chip SRAM and integrated I/O peripheralsa 240-lead MQFP package, thermally enhanced MQFP, 225-ball complete system-on-a-chip plastic ball grid array (PBGA) Integrated multiprocessing features Lead (Pb) free packages. For more information, see Ordering Guide on Page 52. KEY FEATURESPROCESSOR CORE 50 MIPS, 20 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance CORE PROCESSOR DUAL-PORTED SRAM INSTRUCTION JTAG TIMER TWO INDEPENDENT 7 CACHE DUAL-PORTED BLOCKS TEST AND 32 48-BIT EMULATION PROCESSOR PORT I/O PORT ADDR DATA ADDR DATA DATA ADDR ADDR DATA DAG1 DAG2 PROGRAM 8 4 32 8 4 24 SEQUENCER EXTERNAL PORT IOD IOA 24 48 17 PM ADDRESS BUS 32 ADDR BUS DM ADDRESS BUS 32 MUX MULTIPROCESSOR INTERFACE 48 PM DATA BUS BUS 48 DATA BUS CONNECT 40/32 DM DATA BUS MUX (PX) HOST PORT S DATA IOP 4 DMA REGISTER REGISTERS FILE CONTROLLER (MEMORY 6 MAPPED) BARREL 16 40-BIT MULT ALU SHIFTER CONTROL, SERIAL PORTS 6 STATUS AND (2) DATA BUFFERS I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com BLOCK 0 BLOCK 1ADSP-21061/ADSP-21061L TABLE OF CONTENTS Summary ............................................................... 1 ADSP-21061L Specifications ..................................... 17 Key FeaturesProcessor Core ................................. 1 Operating Conditions (3.3 V) ................................. 17 General Description ................................................. 3 Electrical Characteristics (3.3 V) ............................. 17 SHARC Family Core Architecture ............................ 3 Internal Power Dissipation (3.3 V) .......................... 18 Memory and I/O Interface Features ........................... 4 External Power Dissipation (3.3 V) .......................... 19 Porting Code From the ADSP-21060 or Absolute Maximum Ratings ................................... 20 ADSP-21062 ..................................................... 7 ESD Caution ...................................................... 20 Development Tools ............................................... 7 Package Marking Information ................................ 20 Additional Information .......................................... 8 Timing Specifications ........................................... 20 Related Signal Chains ............................................ 8 Test Conditions .................................................. 43 Pin Function Descriptions ......................................... 9 Environmental Conditions .................................... 46 Target Board Connector For EZ-ICE Probe ............... 12 225-Ball PBGA Pin Configurations ............................. 47 ADSP-21061 Specifications ...................................... 14 240-Lead MQFP Pin Configurations ........................... 49 Operating Conditions (5 V) ................................... 14 Outline Dimensions ................................................ 50 Electrical Characteristics (5 V) ............................... 14 Surface-Mount Design .......................................... 52 Internal Power Dissipation (5 V) ............................ 15 Ordering Guide ..................................................... 52 External Power Dissipation (5 V) ............................ 16 REVISION HISTORY 5/13Rev C to Rev D Updated Development Tools .......................................7 Added Related Signal Chains .......................................8 Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and ADSP-21061LKS-176 models from Ordering Guide ........ 52 GENERAL NOTE This data sheet represents production released specifications for the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for 33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The product nameADSP-21061 is used throughout this data sheet to represent all devices, except where expressly noted. Rev. D Page 2 of 52 May 2013