SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY KEY FEATURESPROCESSOR CORE High performance signal processor for communications, 40 MIPS, 25 ns instruction rate, single-cycle instruction graphics and imaging applications execution Super Harvard Architecture 120 MFLOPS peak, 80 MFLOPS sustained performance 4 independent buses for dual data fetch, instruction fetch, Dual data address generators with modulo and bit-reverse and nonintrusive I/O addressing) 32-bit IEEE floating-point computation unitsmultiplier, Efficient program sequencing with zero-overhead looping: ALU, and shifter Single-cycle loop setup Dual-ported on-chip SRAM and integrated I/O peripheralsa IEEE JTAG Standard 1149.1 Test Access Port and on-chip complete system-on-a-chip emulation Integrated multiprocessing features 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data 240-lead thermally enhanced MQFP PQ4 package, 225-ball format plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages CORE PROCESSOR DUAL-PORTED SRAM INSTRUCTION JTAG TIMER TWO INDEPENDENT 7 CACHE DUAL-PORTED BLOCKS TEST AND 32 48-BIT EMULATION PROCESSOR PORT I/O PORT ADDR DATA ADDR DATA DATA ADDR ADDR DATA DAG1 DAG2 PROGRAM 8 4 32 8 4 24 SEQUENCER EXTERNAL PORT IOD IOA 24 48 17 PM ADDRESS BUS 32 ADDR BUS DM ADDRESS BUS 32 MUX MULTIPROCESSOR INTERFACE 48 PM DATA BUS BUS 48 DATA BUS CONNECT 40/32 DM DATA BUS MUX (PX) HOST PORT S DATA DMA 4 IOP REGISTER CONTROLLER REGISTERS FILE 6 (MEMORY SERIAL PORTS MAPPED) BARREL 16 40-BIT 6 MULT ALU (2) SHIFTER CONTROL, STATUS AND 36 LINK PORTS DATA BUFFERS (6) I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com BLOCK 0 BLOCK 1ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PARALLEL COMPUTATIONS HOST PROCESSOR INTERFACE TO 16- AND 32-BIT MICROPROCESSORS Single-cycle multiply and ALU operations in parallel with dual memory read/writes and instruction fetch Host can directly read/write ADSP-2106x internal memory Multiply with add and subtract for accelerated FFT butterfly and IOP registers computation MULTIPROCESSING UP TO 4M BIT ON-CHIP SRAM Glueless connection for scalable DSP multiprocessing Dual-ported for independent access by core processor and architecture DMA Distributed on-chip bus arbitration for parallel bus connect of up to six ADSP-2106xs plus host OFF-CHIP MEMORY INTERFACING Six link ports for point-to-point connectivity and array 4 gigawords addressable multiprocessing Programmable wait state generation, page-mode DRAM 240 MBps transfer rate over parallel bus support 240 MBps transfer rate over link ports DMA CONTROLLER SERIAL PORTS 10 DMA channels for transfers between ADSP-2106x internal Two 40 Mbps synchronous serial ports with companding memory and external memory, external peripherals, host hardware processor, serial ports, or link ports Independent transmit and receive functions Background DMA transfers at up to 40 MHz, in parallel with full-speed processor execution Table 1. ADSP-2106x SHARC Processor Family Features Feature ADSP-21060 ADSP-21062 ADSP-21060L ADSP-21062L ADSP-21060C ADSP-21060LC SRAM 4M bits 2M bits 4M bits 2M bits 4M bits 4M bits Operating Voltage 5 V 5 V 3.3 V 3.3 V 5 V 3.3 V Instruction 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz Rate 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz MQFP PQ4 MQFP PQ4 MQFP PQ4 MQFP PQ4 Package PBGA PBGA PBGA PBGA CQFP CQFP Rev. H Page 2 of 64 March 2013