a DSP Microcomputer ADSP-21065L SUMMARY SDRAM Controller for Glueless Interface to Low Cost High Performance Signal Computer for Communica- External Memory ( 66 MHz) tions, Audio, Automotive, Instrumentation and 64M Words External Address Range Industrial Applications 12 Programmable I/O Pins and Two Timers with Event Super Harvard Architecture Computer (SHARC ) Capture Options Four Independent Buses for Dual Data, Instruction, Code-Compatible with ADSP-2106x Family and I/O Fetch on a Single Cycle 208-Lead MQFP or 196-Ball Mini-BGA Package 32-Bit Fixed-Point Arithmetic 32-Bit and 40-Bit Floating- 3.3 Volt Operation Point Arithmetic Flexible Data Formats and 40-Bit Extended Precision 544 Kbits On-Chip SRAM Memory and Integrated I/O 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Peripheral Floating-Point Data Formats 2 I S Support, for Eight Simultaneous Receive and Trans- 32-Bit Fixed-Point Data Format, Integer and Fractional, mit Channels with Dual 80-Bit Accumulators KEY FEATURES Parallel Computations 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Single-Cycle Multiply and ALU Operations in Parallel with Performance Dual Memory Read/Writes and Instruction Fetch User-Configurable 544 Kbits On-Chip SRAM Memory Multiply with Add and Subtract for Accelerated FFT But- Two External Port, DMA Channels and Eight Serial terfly Computation Port, DMA Channels 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles) CORE PROCESSOR DUAL-PORTED SRAM JTAG 7 INSTRUCTION TWO INDEPENDENT TEST & CACHE DUAL-PORTED BLOCKS EMULATION 32 48 BIT PROCESSOR PORT I/O PORT ADDR DATA DATA ADDR ADDR DATA ADDR DATA EXTERNAL DAG1 DAG2 PROGRAM PORT 8 4 32 8 4 24 SEQUENCER SDRAM IOD IOA INTERFACE 48 24 PM ADDRESS BUS 17 24 ADDR BUS 32 DM ADDRESS BUS MUX MULTIPROCESSOR INTERFACE PM DATA BUS 48 32 BUS DATA BUS CONNECT 40 DM DATA BUS MUX (PX) HOST PORT 4 DMA DATA IOP CONTROLLER REGISTER REGISTERS FILE (MEMORY MAPPED) (2 Rx, 2Tx) 16 40 BIT BARREL SPORT 0 MULTIPLIER ALU CONTROL, 2 (I S) SHIFTER STATUS, TIMER & (2 Rx, 2Tx) DATA BUFFERS SPORT 1 2 (I S) I/O PROCESSOR Figure 1. Functional Block Diagram SHARC is a registered trademark of Analog Devices, Inc. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective companies. BLOCK 0 BLOCK 1ADSP-21065L 544 Kbits Configurable On-Chip SRAM Host Processor Interface Dual-Ported for Independent Access by Core Processor Efficient Interface to 8-, 16-, and 32-Bit Microprocessors and DMA Host Can Directly Read/Write ADSP-21065L IOP Registers Configurable in Combinations of 16-, 32-, 48-Bit Data and Multiprocessing Program Words in Block 0 and Block 1 Distributed On-Chip Bus Arbitration for Glueless, Parallel DMA Controller Bus Connect Between Two ADSP-21065Ls Plus Host Ten DMA ChannelsTwo Dedicated to the External Port 132 Mbytes/s Transfer Rate Over Parallel Bus and Eight Dedicated to the Serial Ports Serial Ports Background DMA Transfers at up to 66 MHz, in Parallel Independent Transmit and Receive Functions with Full Speed Processor Execution Programmable 3-Bit to 32-Bit Serial Word Width Performs Transfers Between: 2 I S Support Allowing Eight Transmit and Eight Receive Internal RAM and Host Channels Internal RAM and Serial Ports Glueless Interface to Industry Standard Codecs Internal RAM and Master or Slave SHARC TDM Multichannel Mode with -Law/A-Law Hardware Internal RAM and External Memory or I/O Devices Companding External Memory and External Devices Multichannel Signaling Protocol 2 REV. C