SHARC Processor ADSP-21161N Integrated peripheralsintegrated I/O processor, 1M bit on- SUMMARY chip dual-ported SRAM, SDRAM controller, glueless multi- High performance 32-Bit DSPapplications in audio, medi- processing features, and I/O ports (serial, link, external cal, military, wireless communications, graphics, imaging, bus, SPI, and JTAG) motor-control, and telephony ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit Super Harvard Architecturefour independent buses for floating-point formats dual data fetch, instruction fetch, and nonintrusive zero- 100 MHz/110 MHz core instruction rate overhead I/O Single-cycle instruction execution, including SIMD opera- Code compatible with all other sharc family DSPs tions in both computational units Single-instruction multiple-data (SIMD) computational archi- Up to 660 MFLOPs peak and 440 MFLOPs sustained tecturetwo 32-bit IEEE floating-point computation units, performance each with a multiplier, ALU, shifter, and register file 2 225-ball 17 mm 17 mm CSP BGA package Serial ports offer I S support via 8 programmable and simul- taneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio DUAL-PORTED SRAM CORE PROCESSOR 6 JTAG TEST TWO INDEPENDENT INSTRUCTION AND EMULATION DUAL-PORTED BLOCKS CACHE TIMER I/O PORT 32 u 48-BIT PROCESSOR PORT 12 GPIO DATA ADDR DATA ADDR FLAGS ADDR DATA DATA ADDR DAG1 DAG2 8 PROGRAM SDRAM 8 u 4 u 32 8 u 4 u 32 SEQUENCER CONTROLLER IOD IOA EXTERNAL PORT 64 18 32 24 ADDR BUS PM ADDRESS BUS 32 MUX DM ADDRESS BUS 64 MULTIPROCESSOR BUS PM DATA BUS INTERFACE CONNECT 64 (PX) DM DATA BUS 32 DATA BUS MUX DATA DATA REGISTER REGISTER HOST PORT FILE FILE (PEX) (PEY) BARREL BARREL 16 u 40-BIT 16 u 40-BIT SHIFTER SHIFTER MULT MULT 5 DMA IOP CONTROLLER ALU ALU REGISTERS 16 (MEMORY MAPPED) SERIAL PORTS (4) 20 CONTROL, LINK PORTS (2) STATUS, & 4 DATA BUFFERS SPI PORTS (1) S I/O PROCESSOR Figure 1. ADSP-21161N Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Technical Support www.analog.com BLOCK 0 BLOCK 1ADSP-21161N TABLE OF CONTENTS Summary ............................................................... 1 Absolute Maximum Ratings ................................... 19 General Description ................................................. 3 ESD Caution ...................................................... 19 ADSP-21161N Family Core Architecture .................... 3 Timing Specifications ........................................... 19 ADSP-21161N Memory and I/O Interface Features ....... 5 Power Dissipation ............................................... 20 Development Tools ............................................... 9 Output Drive Currents ......................................... 54 Additional Information ........................................ 10 Test Conditions .................................................. 54 Related Signal Chains .......................................... 10 Environmental Conditions .................................... 55 Pin Function Descriptions ....................................... 11 225-Ball CSP BGA Ball Configurations ....................... 56 Boot Modes ....................................................... 16 Outline Dimensions ................................................ 58 Specifications ........................................................ 17 Surface-Mount Design .......................................... 58 Operating Conditions .......................................... 17 Ordering Guide ..................................................... 58 Electrical Characteristics ....................................... 18 Package Information ........................................... 19 REVISION HISTORY 1/13Rev. B to Rev. C Updated Development Tools ...................................... 9 Added section, Related Signal Chains .......................... 10 Added footnote 3 to Table 16 in Memory Read Bus Master .................................... 27 Rev. C Page 2 of 60 January 2013