SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor Single-instruction multiple-data (SIMD) computational archi- optimized for high performance audio processing tecturetwo 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational Code compatibilityat assembly level, uses the same units, each with a multiplier, ALU, shifter, and register file instruction set as other SHARC DSPs High bandwidth I/Oa parallel port, an SPI port, 6 serial Processes high performance audio while enabling low ports, a Digital application interface (DAI), and JTAG system costs DAI incorporates two precision clock generators (PCGs), an Audio decoders and postprocessor algorithms support input data port (IDP) that includes a parallel data acquisi- nonvolatile memory that can be configured to contain a tion port (PDAP), and 3 programmable timers, all under combination of PCM 96 kHz, Dolby Digital, Dolby Digital software control by the signal routing unit (SRU) Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMA- On-chip memoryup to 2M bits on-chip SRAM and a dedi- PRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and cated 4M bits on-chip mask-programmable ROM DTS Neo:6 The ADSP-2126x processors are available with a 150 MHz or a Various multichannel surround sound decoders are con- 200 MHz core instruction rate. For complete ordering tained in ROM. For configurations of decoder algorithms, information, see Ordering Guide on Page 45. see Table 3 on Page 4. CORE PROCESSOR DUAL PORTED MEMORY DUAL PORTED MEMORY BLOCK 0 BLO CK 1 INSTRUCTION CACHE SRAM SRAM TIMER 1M BIT ROM 1M BIT ROM 32 48-BIT 2M BIT 2M BIT DAG1 DAG2 PROGRAM 8 4 32 8 4 32 SEQUENCER ADDR DATA ADDR DATA PM ADDRESS BUS 32 DM ADDRESS BUS 32 64 PM DATA BUS 64 DM DATA BUS IOD IOA (32) (19) DMA CONTROLLER PX REGISTER 4 22 CHANNELS GPIO FLAGS/ PROCESSING PROCESSING ELEMENT IRQ/TIMEXP ELEMENT 4 (PEX) (PEY) SPI PORT (1) 16 ADDRESS/ DATA BUS/GPIO 3 6 CONTROL/GPIO SERIAL PORTS (6) JTAG TEST & EMULATION PARALLEL IOP PORT REGISTERS 20 SIGNAL INPUT (MEMORY MAPPED) RO UTI NG DATA PORTS (8) UNIT PARALLEL DATA CONTROL, ACQUISITION PORT STATUS, DATA BUFFERS PRECISION CLOCK GENERATORS (2) S 3 PERIPHERAL TI MERS (3) DIGITAL AUDIO INTERFACE I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2012 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-21261/ADSP-21262/ADSP-21266 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 15 General Description ................................................. 3 Maximum Power Dissipation ................................. 15 Family Core Architecture ........................................ 3 Absolute Maximum Ratings ................................... 15 Memory and I/O Interface Features ........................... 4 Timing Specifications ........................................... 15 Target Board JTAG Emulator Connector .................... 8 Output Drive Currents ......................................... 37 Development Tools ............................................... 8 Test Conditions .................................................. 37 Additional Information .......................................... 9 Capacitive Loading .............................................. 37 Related Signal Chains ............................................ 9 Environmental Conditions .................................... 38 Pin Function Descriptions ....................................... 10 Thermal Characteristics ........................................ 38 Address Data Pins as Flags .................................... 13 144-Lead LQFP Pin Configurations ............................ 39 Core Instruction Rate to CLKIN Ratio Modes ............ 13 136-Ball BGA Pin Configurations ............................... 40 Address Data Modes ............................................ 13 Outline Dimensions ................................................ 43 Product Specifications ............................................. 14 Surface-Mount Design .......................................... 44 Operating Conditions .......................................... 14 Automotive Products .............................................. 45 Electrical Characteristics ....................................... 14 Ordering Guide ..................................................... 45 Package Information ........................................... 15 REVISION HISTORY 12/12Rev. F to Rev. G Corrected Long Word Memory Space in Table 4 in Memory and I/O Interface Features ...............................4 Updated Development Tools .......................................8 Added section, Related Signal Chains .............................9 Changed the package designator in Figure 36 from BC-136 to BC-136-1. This change in no way affects form, fit, or function. See Outline Dimensions ........................................... 43 Updated Ordering Guide .......................................... 45 Rev. G Page 2 of 48 December 2012