SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor S/PDIF-compatible digital audio receiver/transmitter optimized for high performance audio processing 8 channels of asynchronous sample rate converters (SRC) Single-instruction, multiple-data (SIMD) computational 16 PWM outputs configured as four groups of four outputs architecture ROM-based security features include: On-chip memory3M bits of on-chip SRAM JTAG access to memory permitted with a 64-bit key Code compatible with all other members of the SHARC family Protected memory regions that can be assigned to limit access under program control to sensitive code The ADSP-2136x processors are available with up to 333 MHz PLL has a wide variety of software and hardware multi- core instruction rate with unique audiocentric peripherals plier/divider ratios such as the digital applications interface, S/PDIF trans- ceiver, DTCP (digital transmission content protection Available in 136-ball CSP BGA and 144-lead LQFP EP protocol), serial ports, precision clock generators, and packages more. For complete ordering information, see Ordering Guide on Page 56. Internal Memory SIMD Core Block 0 Block 1 Block 2 Block 3 RAM/ROM RAM/ROM RAM RAM Instruction 5 stage Cache Sequencer B2D B0D B1D B3D 64-BIT 64-BIT 64-BIT 64-BIT S DAG1/2 Timer DMD 64-BIT DMD 64-BIT PEx PEy Core Bus Internal Memory I/F Cross Bar PMD 64-BIT PMD 64-BIT FLAGx/IRQx/ JTAG TMREXP PERIPHERAL BUS IOD 32-BIT 32-BIT MTM/ DTCP IOD BUS PERIPHERAL BUS CORE TIMER ASRC S/PDIF PCG PDAP/ SPORT Core PWM SPI B PP SPI FLAGS 2-0 3 -0 Tx/Rx A-B Flags IDP7-0 5-0 3-0 DAI Routing/Pins PP Pin MUX DAI Peripherals Peripherals Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.comADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 ESD Caution ...................................................... 16 Dedicated Audio Components .................................... 1 Maximum Power Dissipation ................................. 16 General Description ................................................. 3 Absolute Maximum Ratings ................................... 16 SHARC Family Core Architecture ............................ 4 Timing Specifications ........................................... 16 Family Peripheral Architecture ................................ 6 Output Drive Currents ......................................... 46 I/O Processor Features ........................................... 8 Test Conditions .................................................. 46 System Design ...................................................... 8 Capacitive Loading .............................................. 46 Development Tools ............................................... 9 Thermal Characteristics ........................................ 47 Additional Information ........................................ 10 144-Lead LQFP EP Pin Configurations ....................... 48 Related Signal Chains .......................................... 10 136-Ball BGA Pin Configurations ............................... 50 Pin Function Descriptions ....................................... 11 Package Dimensions ............................................... 53 Specifications ........................................................ 14 Surface-Mount Design .......................................... 54 Operating Conditions .......................................... 14 Automotive Products .............................................. 55 Electrical Characteristics ....................................... 15 Ordering Guide ..................................................... 56 Package Information ........................................... 16 REVISION HISTORY 7/13Revision I to Revision J Updated Development Tools .......................................9 Added Nominal Value column in Operating Conditions .. 14 Changed Max values in Table 30 in Pulse-Width Modulation Generators ............................................................35 Updated Ordering Guide .......................................... 56 Rev. J Page 2 of 60 July 2013