SHARC Processor ADSP-21467/ADSP-21469 SUMMARY High performance 32-bit/40-bit floating-point processor Available with unique audiocentric peripherals such as the optimized for high performance audio processing digital applications interface, DTCP (digital transmission content protection protocol), serial ports, precision clock Single-instruction, multiple-data (SIMD) computational generators, S/PDIF transceiver, asynchronous sample rate architecture converters, input data port, and more. 5 Mbits of on-chip RAM, 4 Mbits of on-chip ROM For complete ordering information, see Ordering Guide on Up to 450 MHz operating frequency Page 74 Qualified for automotive applications, see Automotive Prod- ucts on Page 74 Code compatible with all other members of the SHARC family INTERNAL MEMORY SIMD CORE BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3 RAM/ROM RAM/ROM RAM RAM INSTRUCTION 5 STAGE CACHE SEQUENCER B0D B1D B2D B3D 64-BIT 64-BIT 64-BIT 64-BIT DAG1/2 TIMER S DMD DMD 64-BIT 64-BIT CORE BUS PEX PEY INTERNAL MEMORY INTERFACE CROSS BAR PMD PMD 64-BIT 64-BIT FLAGx/IRQx/ THERMAL IOD0 32-BIT EPD BUS 64-BIT JTAG TMREXP DIODE IOD1 32-BIT PERIPHERAL BUS 32-BIT IOD0 BUS FFT DTCP/ FIR MTM IIR PERIPHERAL BUS EP SPEP BUS LINK PDAP/ CORE PCG TIMER S/PDIF PCG ASRC SPORT CORE PWM DDR2 TWI SPI/B UART MLB PORT AMI IDP FLAGS C-D 1-0 TX/RX A-D 3-0 7-0 FLAGS 3-0 CTL 7-0 1-0 DPI ROUTING/PINS DAI ROUTING/PINS EXTERNAL PORT PIN MUX EXTERNAL PORT DPI PERIPHERALS DAI PERIPHERALS PERIPHERALS Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 2013 Analog Devices, Inc. All rights reserved. or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Technical Support www.analog.comADSP-21467/ADSP-21469 TABLE OF CONTENTS Summary ............................................................... 1 ESD Sensitivity ................................................... 23 General Description ................................................. 3 Timing Specifications ........................................... 23 Family Core Architecture ........................................ 4 Test Conditions .................................................. 62 Family Peripheral Architecture ................................ 7 Output Drive Currents ......................................... 62 System Design .................................................... 10 Capacitive Loading .............................................. 63 Development Tools ............................................. 11 Thermal Characteristics ........................................ 65 Additional Information ........................................ 12 CSP BGA Ball AssignmentAutomotive Models .......... 67 Related Signal Chains .......................................... 12 CSP BGA Ball AssignmentStandard Models .............. 70 Pin Function Descriptions ....................................... 13 Outline Dimensions ................................................ 73 Specifications ........................................................ 19 Surface-Mount Design .......................................... 73 Operating Conditions .......................................... 19 Automotive Products .............................................. 74 Electrical Characteristics ....................................... 20 Ordering Guide ..................................................... 74 Absolute Maximum Ratings .................................. 22 Package Information ........................................... 22 REVISION HISTORY 3/13Rev. A to Rev. B Added BOOT CFG2 signal to Table 62 (CSP BGA Ball Assignment) in CSP BGA Ball Assignment Updated Development Tools .................................... 11 Standard Models .................................................... 70 Revised termination description, AMI MS pin description, 0-1 Added footnote to Table 62 Chip ID description, and V pin description in DD THD (CSP BGA Ball Assignment) in CSP BGA Ball Assignment Pin Function Descriptions ....................................... 13 Standard Models .................................................... 70 Corrected parameter from I to I in DD-INTYP DD INT Corrected ball assignments in Figure 61 in CSP BGA Ball Electrical Characteristics .......................................... 20 AssignmentStandard Models .................................. 70 Modified Total Power Dissipation .............................. 21 Added leaded model ADSP-21469BBC-3 to Corrected unit values for t , t , and t in CLKRST PLLRST CORERST Ordering Guide ..................................................... 74 Table 18 in Power-Up Sequencing ............................. 25 Modified note in Figure 8 in Clock Signals ................... 26 Added footnote 3 to Table 31in AMI Read ................... 35 Changed min value for parameter t from t 2 to 4 DLACLK LCLK in Link Ports ......................................................... 39 Added Table 35 in Link Ports .................................... 39 Added Figure 24 in Link Ports .................................. 39 Relabeled table tile for Table 36 in Link Ports ................ 39 Relabeled figure title for Figure 25 in Link Ports ............ 39 Changed Max values in Table 46 in Pulse-Width Modulation (PWM) Generators ................................................ 51 Added BOOT CFG2 signal to Table 61 (CSP BGA Ball Assignment) in CSP BGA Ball Assignment Automotive Models ................................................ 67 Revised footnote for Table 61 (CSP BGA Ball Assignment) in CSP BGA Ball Assignment Automotive Models ................................................ 67 Corrected ball assignments in Figure 60 in CSP BGA Ball AssignmentAutomotive Models ............................. 67 Rev. B Page 2 of 76 March 2013