a DSP Microcomputer ADSP-2183 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE POWERDOWN PROGRAMMABLE 19 ns Instruction Cycle Time from 26.32 MHz Crystal CONTROL I/O 3.3 Volts FLAGS MEMORY DATA ADDRESS 52 MIPS Sustained Performance GENERATORS PROGRAM PROGRAM DATA SEQUENCER BYTE DMA MEMORY MEMORY DAG 1 DAG 2 CONTROLLER Single-Cycle Instruction Execution EXTERNAL Single-Cycle Context Switch ADDRESS BUS PROGRAM MEMORY ADDRESS 3-Bus Architecture Allows Dual Operand Fetches in DATA MEMORY ADDRESS Every Instruction Cycle Multifunction Instructions PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby DATA MEMORY DATA EXTERNAL Power Dissipation with 300 Cycle Recovery from DATA BUS Power-Down Condition ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL DMA Low Power Dissipation in Idle Mode SPORT 0 SPORT 1 ALU MAC SHIFTER PORT DMA BUS INTEGRATION ADSP-2100 BASE ARCHITECTURE ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as GENERAL DESCRIPTION 16K Words On-Chip Program Memory RAM The ADSP-2183 is a single-chip microcomputer optimized for 16K Words On-Chip Data Memory RAM digital signal processing (DSP) and other high speed numeric Dual Purpose Program Memory for Both Instruction processing applications. and Data Storage The ADSP-2183 combines the ADSP-2100 family base architec- Independent ALU, Multiplier/Accumulator, and Barrel ture (three computational units, data address generators and Shifter Computational Units a program sequencer) with two serial ports, a 16-bit internal Two Independent Data Address Generators DMA port, a byte DMA port, a programmable timer, Flag I/O, Powerful Program Sequencer Provides Zero Overhead Looping extensive interrupt capabilities, and on-chip program and Conditional Instruction Execution data memory. Programmable 16-Bit Interval Timer with Prescaler The ADSP-2183 integrates 80K bytes of on-chip memory con- 128-Lead LQFP, 144-Ball Mini-BGA figured as 16K words (24-bit) of program RAM, and 16K words SYSTEM INTERFACE (16-bit) of data RAM. Power-down circuitry is also provided to 16-Bit Internal DMA Port for High Speed Access to meet the low power needs of battery operated portable equipment. On-Chip Memory The ADSP-2183 is available in 128-lead LQFP, and 144-Ball 4 MByte Memory Interface for Storage of Data Tables Mini-BGA packages. and Program Overlays In addition, the ADSP-2183 supports new instructions, which 8-Bit DMA to Byte Memory for Transparent include bit manipulationsbit set, bit clear, bit toggle, bit test Program and Data Memory Transfers new ALU constants, new multiplication instruction (x squared), I/O Memory Interface with 2048 Locations Supports biased rounding, result free ALU operations, I/O memory trans- Parallel Peripherals fers and global interrupt masking, for increased flexibility. Programmable Memory Strobe and Separate I/O Memory Space Permits Glueless System Design Fabricated in a high speed, double metal, low power, CMOS Programmable Wait State Generation process, the ADSP-2183 operates with a 19 ns instruction cycle Two Double-Buffered Serial Ports with Companding time. Every instruction can execute in a single processor cycle. Hardware and Automatic Data Buffering The ADSP-2183s flexible architecture and comprehensive Automatic Booting of On-Chip Program Memory from instruction set allow the processor to perform multiple opera- Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port tions in parallel. In one processor cycle the ADSP-2183 can: Six External Interrupts Generate the next program address 13 Programmable Flag Pins Provide Flexible System Fetch the next instruction Signaling Perform one or two data moves ICE-Port Emulator Interface Supports Debugging Update one or two data address pointers in Final Systems Perform a computational operation ICE-Port is a trademark of Analog Devices, Inc. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADSP-2183 This takes place while the processor continues to: ARCHITECTURE OVERVIEW Receive and transmit data through the two serial ports The ADSP-2183 instruction set provides flexible data moves Receive and/or transmit data through the internal DMA port and multifunction (one or two data moves with a computation) Receive and/or transmit data through the byte DMA port instructions. Every instruction can be executed in a single pro- Decrement timer cessor cycle. The ADSP-2183 assembly language uses an alge- braic syntax for ease of coding and readability. A comprehensive Development System set of development tools supports program development. The ADSP-2100 Family Development Software, a complete Figure 1 is an overall block diagram of the ADSP-2183. The set of tools for software and hardware system development, processor contains three independent computational units: the supports the ADSP-2183. The assembler has an algebraic syntax ALU, the multiplier/accumulator (MAC) and the shifter. The that is easy to program and debug. The linker combines object computational units process 16-bit data directly and have provi- files into an executable file. The simulator provides an interactive sions to support multiprecision computations. The ALU per- instruction-level simulation with a reconfigurable user interface forms a standard set of arithmetic and logic operations division to display different portions of the hardware environment. primitives are also supported. The MAC performs single-cycle The EZ-KIT Lite is a hardware/software kit offering a com- multiply, multiply/add and multiply/subtract operations with plete development environment for the ADSP-21xx family: 40 bits of accumulation. The shifter performs logical and arith- an ADSP-2189M evaluation board with PC monitor software metic shifts, normalization, denormalization and derive plus Assembler, Linker, Simulator and PROM Splitter software. exponent operations. The shifter can be used to efficiently The ADSP-2189M evaluation board is a low-cost, easy to use implement numeric format control including multiword and hardware platform on which you can quickly get started with block floating-point representations. your DSP software design. The EZ-KIT Lite include the The internal result (R) bus connects the computational units so following features: that the output of any unit may be the input of any unit on the 35.7 MHz ADSP-2189M next cycle. Full 16-bit Stereo Audio I/O with AD73322 CODEC The ADSP-21xx family DSPs contain a shadow register that is RS-232 Interface useful for single cycle context switching of the processor. EZ-ICE Connector for Emulator Control DSP Demo Programs A powerful program sequencer and two dedicated data address Evaluation Suite of VisualDSP generators ensure efficient delivery of operands to these compu- tational units. The sequencer supports conditional jumps, sub- The ADSP-218x EZ-ICE Emulator aids in the hardware debug- routine calls and returns in a single cycle. With internal loop ging of ADSP-218x systems. The ADSP-218x integrates on-chip counters and loop stacks, the ADSP-2183 executes looped code emulation support with a 14-pin ICE-Port interface. This inter- with zero overhead no explicit jump instructions are required to face provides a simpler target board connection requiring fewer maintain loops. mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. The ADSP-218x device need not be removed Two data address generators (DAGs) provide addresses for from the target system when using the EZ-ICE, nor are any simultaneous dual operand fetches (from data memory and adapters needed. Due to the small footprint of the EZ-ICE program memory). Each DAG maintains and updates four connector, emulation can be supported in final board designs. address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of The EZ-ICE performs a full range of functions, including: four possible modify registers. A length value may be associated In-target operation with each pointer to implement automatic modulo addressing Up to 20 breakpoints for circular buffers. Single-step or full-speed operation Efficient data transfer is achieved with the use of five internal Registers and memory values can be examined and altered buses: PC upload and download functions Instruction-level emulation of program booting and execution Program Memory Address (PMA) Bus Complete assembly and disassembly of instructions Program Memory Data (PMD) Bus C source-level debugging Data Memory Address (DMA) Bus Data Memory Data (DMD) Bus (See Designing An EZ-ICE-Compatible Target System section Result (R) Bus of this data sheet for exact specifications of the EZ-ICE target The two address buses (PMA and DMA) share a single external board connector.) address bus, allowing memory to be expanded off-chip, and the Additional Information two data buses (PMD and DMD) share a single external data This data sheet provides a general overview of ADSP-2183 bus. Byte memory space and I/O memory space also share the functionality. For additional information on the architecture and external buses. instruction set of the processor, refer to the ADSP-2100 Family Program memory can store both instructions and data, permit- Users Manual, Third Edition. For more information about the ting the ADSP-2183 to fetch two operands in a single cycle, development tools, refer to the ADSP-2100 Family Development one from program memory and one from data memory. The Tools Data Sheet. ADSP-2183 can fetch an operand from program memory and the next instruction in the same cycle. EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. 2 REV. C