a DSP Microcomputer ADSP-2184 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE POWER-DOWN CONTROL FULL MEMORY 25 ns Instruction Cycle Time 40 MIPS Sustained MODE MEMORY PROGRAMMABLE Performance DATA ADDRESS I/O PROGRAM EXTERNAL GENERATORS 4K 3 24 4K 3 16 AND Single-Cycle Instruction Execution SEQUENCER PROGRAM DATA ADDRESS FLAGS DAG 1 DAG 2 MEMORY MEMORY BUS Single-Cycle Context Switch EXTERNAL DATA 3-Bus Architecture Allows Dual Operand Fetches in PROGRAM MEMORY ADDRESS BUS Every Instruction Cycle DATA MEMORY ADDRESS BYTE DMA CONTROLLER Multifunction Instructions PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby OR DATA MEMORY DATA Power Dissipation with 200 Cycle Recovery from EXTERNAL DATA Power-Down Condition BUS ARITHMETIC UNITS SERIAL PORTS TIMER Low Power Dissipation in Idle Mode INTERNAL ALU SHIFTER SPORT 0 SPORT 1 MAC DMA PORT INTEGRATION ADSP-2100 BASE HOST MODE ARCHITECTURE ADSP-2100 Family Code Compatible, with Instruction Set Extensions 20K Bytes of On-Chip RAM, Configured as Six External Interrupts 4K Words On-Chip Program Memory RAM and 13 Programmable Flag Pins Provide Flexible System 4K Words On-Chip Data Memory RAM Signaling Dual Purpose Program Memory for Both Instruction UART Emulation through Software SPORT Reconfiguration and Data Storage ICE-Port Emulator Interface Supports Debugging Independent ALU, Multiplier/Accumulator and Barrel in Final Systems Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides GENERAL DESCRIPTION Zero Overhead Looping Conditional Instruction The ADSP-2184 is a single-chip microcomputer optimized for Execution digital signal processing (DSP) and other high speed numeric Programmable 16-Bit Interval Timer with Prescaler processing applications. 100-Lead LQFP The ADSP-2184 combines the ADSP-2100 family base archi- tecture (three computational units, data address generators and SYSTEM INTERFACE a program sequencer) with two serial ports, a 16-bit internal 16-Bit Internal DMA Port for High Speed Access to DMA port, a byte DMA port, a programmable timer, Flag I/O, On-Chip Memory (Mode Selectable) extensive interrupt capabilities and on-chip program and data 4 MByte Byte Memory Interface for Storage of Data memory. Tables and Program Overlays (Made Selectable) 8-Bit DMA to Byte Memory for Transparent Program The ADSP-2184 integrates 20K bytes of on-chip memory con- and Data Memory Transfers (Mode Selectable) figured as 4K words (24-bit) of program RAM and 4K words I/O Memory Interface with 2048 Locations Supports (16-bit) of data RAM. Power-down circuitry is also provided to Parallel Peripherals (Mode Selectable) meet the low power needs of battery operated portable equip- Programmable Memory Strobe and Separate I/O Memory ment. The ADSP-2184 is available in 100-lead LQFP package. Space Permits Glueless System Design In addition, the ADSP-2184 supports instructions that include (Mode Selectable) bit manipulationsbit set, bit clear, bit toggle, bit test ALU Programmable Wait State Generation constants, multiplication instruction (x squared), biased round- Two Double-Buffered Serial Ports with Companding ing, result free ALU operations, I/O memory transfers, and Hardware and Automatic Data Buffering global interrupt masking for increased flexibility. Automatic Booting of On-Chip Program Memory from Fabricated in a high speed, double metal, low power, CMOS Byte-Wide External Memory, e.g., EPROM, or process, the ADSP-2184 operates with a 25 ns instruction cycle Through Internal DMA Port time. Every instruction can execute in a single processor cycle. ICE-Port is a trademark of Analog Devices, Inc. All trademarks are the property of their respective holders. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADSP-2184 The EZ-ICE performs a full range of functions, including: The ADSP-21xx family DSPs contain a shadow bank register that is useful for single cycle context switching of the processor. In-target operation Up to 20 breakpoints The ADSP-2184s flexible architecture and comprehensive Single-step or full-speed operation instruction set allow the processor to perform multiple opera- Registers and memory values can be examined and altered tions in parallel. In one processor cycle the ADSP-2184 can: PC upload and download functions Generate the next program address Instruction-level emulation of program booting and execution Fetch the next instruction Complete assembly and disassembly of instructions Perform one or two data moves C source-level debugging Update one or two data address pointers See Designing An EZ-ICE-Compatible Target System in the Perform a computational operation ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as This takes place while the processor continues to: well as the Target Board Connector for EZ-ICE Probe section Receive and transmit data through the two serial ports of this data sheet, for the exact specifications of the EZ-ICE Receive or transmit data through the internal DMA port target board connector. Receive or transmit data through the byte DMA port Decrement timer Additional Information This data sheet provides a general overview of ADSP-2184 Development System functionality. For additional information on the architecture and The ADSP-2100 Family Development Software, a complete set instruction set of the processor, refer to the ADSP-2100 Family of tools for software and hardware system development, sup- Users Manual, Third Edition. For more information about the ports the ADSP-2184. The System Builder provides a high level development tools, refer to the ADSP-2100 Family Development method for defining the architecture of systems under develop- Tools Data Sheet. ment. The Assembler has an algebraic syntax that is easy to program and debug. The Linker combines object files into an ARCHITECTURE OVERVIEW executable file. The Simulator provides an interactive instruction- The ADSP-2184 instruction set provides flexible data moves level simulation with a reconfigurable user interface to display and multifunction (one or two data moves with a computation) different portions of the hardware environment. A PROM instructions. Every instruction can be executed in a single pro- Splitter generates PROM programmer compatible files. The cessor cycle. The ADSP-2184 assembly language uses an alge- C Compiler, based on the Free Software Foundations GNU braic syntax for ease of coding and readability. A comprehensive C Compiler, generates ADSP-2184 assembly source code. set of development tools supports program development. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over 100 POWER-DOWN ANSI-standard mathematical and DSP-specific functions. CONTROL FULL MEMORY MODE MEMORY PROGRAMMABLE The EZ-KIT Lite is a hardware/software kit offering a complete DATA ADDRESS I/O GENERATORS PROGRAM 4K 3 24 4K 3 16 EXTERNAL AND development environment for the entire ADSP-21xx family: an SEQUENCER PROGRAM DATA ADDRESS FLAGS DAG 1 DAG 2 BUS MEMORY MEMORY ADSP-218x based evaluation board with PC monitor software EXTERNAL plus Assembler, Linker, Simulator and PROM Splitter software. DATA PROGRAM MEMORY ADDRESS BUS The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware DATA MEMORY ADDRESS BYTE DMA platform on which you can quickly get started with your DSP soft- CONTROLLER PROGRAM MEMORY DATA ware design. The EZ-KIT Lite includes the following features: OR DATA MEMORY DATA EXTERNAL 33 MHz ADSP-2181 DATA BUS Full 16-bit Stereo Audio I/O with AD1847 SoundPort ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL Codec ALU MAC SHIFTER SPORT 0 SPORT 1 DMA PORT RS-232 Interface to PC with Microsoft Windows 3.1 ADSP-2100 BASE HOST MODE Control Software ARCHITECTURE EZ-ICE Connector for Emulator Control Figure 1. Block Diagram DSP Demo Programs Figure 1 is an overall block diagram of the ADSP-2184. The The ADSP-218x EZ-ICE Emulator aids in the hardware debug- processor contains three independent computational units: the ging of an ADSP-2184 system. The emulator consists of hard- ALU, the multiplier/accumulator (MAC) and the shifter. The ware, host computer resident software, and the target board computational units process 16-bit data directly and have provi- connector. The ADSP-2184 integrates on-chip emulation sup- sions to support multiprecision computations. The ALU per- port with a 14-pin ICE-Port interface. This interface provides a forms a standard set of arithmetic and logic operations division simpler target board connection that requires fewer mechanical primitives are also supported. The MAC performs single-cycle clearance considerations than other ADSP-2100 Family EZ- multiply, multiply/add and multiply/subtract operations with ICEs. The ADSP-2184 device need not be removed from the 40 bits of accumulation. The shifter performs logical and arith- target system when using the EZ-ICE, nor are any adapters metic shifts, normalization, denormalization and derive expo- needed. Due to the small footprint of the EZ-ICE connector, nent operations. emulation can be supported in final board designs. The shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc. Windows is a registered trademark of Microsoft Corporation. REV. 0 2