DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained 16-bit internal DMA port for high-speed access to on-chip performance memory (mode selectable) Single-cycle instruction execution 4M-byte memory interface for storage of data tables and pro- gram overlays (mode selectable) Single-cycle context switch 8-bit DMA to byte memory for transparent program and data 3-bus architecture allows dual operand fetches in every memory transfers (mode selectable) instruction cycle Programmable memory strobe and separate I/O memory Multifunction instructions space permits glueless system design Power-down mode featuring low CMOS standby power dissi- Programmable wait state generation pation with 400 CLKIN cycle recovery from power-down condition 2 double-buffered serial ports with companding hardware and automatic data buffering Low power dissipation in idle mode Automatic booting of on-chip program memory from byte- INTEGRATION FEATURES wide external memory, for example, EPROM, or through ADSP-2100 family code compatible (easy to use algebraic internal DMA Port syntax), with instruction set extensions 6 external interrupts Up to 160K bytes of on-chip RAM, configured 13 programmable flag pins provide flexible system signaling Up to 32K words program memory RAM UART emulation through software SPORT reconfiguration Up to 32K words data memory RAM ICE-Port emulator interface supports debugging in final Dual-purpose program memory for both instruction and systems data storage Independent ALU, multiplier/accumulator, and barrel shifter computational units 2 independent data address generators Powerful program sequencer provides zero overhead loop- ing conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA POWER-DOWN CONTROL FULL MEMORY MODE MEMORY PROGRAMMABLE PROGRAM DATA EXTERNAL DATA ADDRESS I/O MEMORY MEMORY ADDRESS GENERATORS PROGRAM AND UP TO BUS UP TO FLAGS DAG1 DAG2 SEQUENCER 32K 24-BIT 32K 16-BIT EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS BYTE DMA DATA MEMORY ADDRESS CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL ALU MAC SHIFTER SPORT0 SPORT1 DMA PORT ADSP-2100 BASE ARCHITECTURE HOST MODE Figure 1. Functional Block Diagram ICE-Port is a trademark of Analog Devices, Inc. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. infringements of patents or other rights of third parties that may result from its use. Tel: 781.329.4700 www.analog.com Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.461.3113 2008 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners.ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L TABLE OF CONTENTS Performance Features ............................................... 1 Specifications ........................................................ 21 Integration Features ................................................. 1 Operating Conditions ........................................... 21 System Interface Features ........................................... 1 Electrical Characteristics ....................................... 21 Table of Contents ..................................................... 2 Absolute Maximum Ratings ................................... 22 Revision History ...................................................... 2 Package Information ............................................ 22 General Description ................................................. 3 ESD Sensitivity ................................................... 22 Architecture Overview ........................................... 3 Timing Specifications ........................................... 22 Modes Of Operation .............................................. 4 Power Supply Current .......................................... 36 Interrupts ........................................................... 5 Power Dissipation ............................................... 37 Low Power Operation ............................................ 6 Output Drive Currents ......................................... 40 System Interface ................................................... 7 Power-Down Current ........................................... 41 Reset .................................................................. 8 Capacitive Loading ADSP-2184L, ADSP-2186L ........ 42 Memory Architecture ............................................ 8 Capacitive Loading ADSP-2185L, ADSP-2187L ........ 42 Bus Request and Bus Grant ................................... 13 Test Conditions .................................................. 43 Flag I/O Pins ..................................................... 13 Environmental Conditions .................................... 43 Instruction Set Description ................................... 14 LQFP Package Pinout ........................................... 44 Development System ........................................... 14 BGA Package Pinout ............................................ 45 Additional Information ........................................ 16 Outline Dimensions ................................................ 46 Pin Descriptions .................................................... 17 Surface Mount Design .......................................... 47 Memory Interface Pins ......................................... 18 Ordering Guide ..................................................... 47 Terminating Unused Pins ..................................... 19 REVISION HISTORY 1/08Rev. C This revision of the ADSP-2184L/ADSP-2185L/ ADSP-2186L/ADSP-2187L processor data sheet combines the ADSP-2184L, ADSP-2185L, ADSP-2186L, and ADSP-2187L. This version also contains new RoHS compliant packages. Rev. C Page 2 of 48 January 2008