a DSP Microcomputer ADSP-2185 FUNCTIONAL BLOCK DIAGRAM FEATURES PERFORMANCE POWER-DOWN CONTROL 30 ns Instruction Cycle Time 33 MIPS Sustained FULL MEMORY MODE MEMORY Performance PROGRAMMABLE DATA ADDRESS I/O 16k 3 24 16k 3 16 EXTERNAL GENERATORS PROGRAM Single-Cycle Instruction Execution AND PROGRAM DATA ADDRESS SEQUENCER FLAGS DAG 1 DAG 2 BUS MEMORY MEMORY Single-Cycle Context Switch EXTERNAL 3-Bus Architecture Allows Dual Operand Fetches in DATA PROGRAM MEMORY ADDRESS BUS Every Instruction Cycle DATA MEMORY ADDRESS BYTE DMA Multifunction Instructions CONTROLLER PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby OR DATA MEMORY DATA Power Dissipation with 100 Cycle Recovery from EXTERNAL DATA Power-Down Condition BUS ARITHMETIC UNITS SERIAL PORTS TIMER Low Power Dissipation in Idle Mode INTERNAL SPORT 0 SPORT 1 ALU MAC SHIFTER DMA PORT INTEGRATION ADSP-2100 BASE HOST MODE ARCHITECTURE ADSP-2100 Family Code Compatible, with Instruction Set Extensions 80K Bytes of On-Chip RAM, Configured as Six External Interrupts 16K Words On-Chip Program Memory RAM and 13 Programmable Flag Pins Provide Flexible System 16K Words On-Chip Data Memory RAM Signaling Dual Purpose Program Memory for Both Instruction UART Emulation through Software SPORT Reconfiguration and Data Storage ICE-Port* Emulator Interface Supports Debugging Independent ALU, Multiplier/Accumulator and Barrel in Final Systems Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides GENERAL NOTE Zero Overhead Looping Conditional Instruction This data sheet represents production grade specifications for Execution the ADSP-2185 (5 V). Programmable 16-Bit Interval Timer with Prescaler 100-Lead TQFP GENERAL DESCRIPTION The ADSP-2185 is a single-chip microcomputer optimized for SYSTEM INTERFACE digital signal processing (DSP) and other high speed numeric 16-Bit Internal DMA Port for High Speed Access to processing applications. On-Chip Memory (Mode Selectable) The ADSP-2185 combines the ADSP-2100 family base archi- 4 MByte Byte Memory Interface for Storage of Data tecture (three computational units, data address generators and Tables & Program Overlays a program sequencer) with two serial ports, a 16-bit internal 8-Bit DMA to Byte Memory for Transparent Program DMA port, a byte DMA port, a programmable timer, Flag I/O, and Data Memory Transfers (Mode Selectable) extensive interrupt capabilities and on-chip program and data I/O Memory Interface with 2048 Locations Supports memory. Parallel Peripherals (Mode Selectable) Programmable Memory Strobe & Separate I/O Memory The ADSP-2185 integrates 80K bytes of on-chip memory con- Space Permits Glueless System Design figured as 16K words (24-bit) of program RAM and 16K words (Mode Selectable) (16-bit) of data RAM. Power-down circuitry is also provided to Programmable Wait State Generation meet the low power needs of battery operated portable equip- Two Double-Buffered Serial Ports with Companding ment. The ADSP-2185 is available in 100-pin TQFP package. Hardware and Automatic Data Buffering In addition, the ADSP-2185 supports new instructions, which Automatic Booting of On-Chip Program Memory from include bit manipulationsbit set, bit clear, bit toggle, bit test Byte-Wide External Memory, e.g., EPROM, or new ALU constants, new multiplication instruction (x squared), Through Internal DMA Port biased rounding, result free ALU operations, I/O memory trans- fers and global interrupt masking, for increased flexibility. *ICE-Port is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 617/329-4700 World Wide Web Site: ADSP-2185 The EZ-ICE * performs a full range of functions, including: Fabricated in a high speed, double metal, low power, 0.5 m CMOS process, the ADSP-2185 operates with a 30 ns instruc- In-target operation tion cycle time. Every instruction can execute in a single proces- Up to 20 breakpoints sor cycle. Single-step or full-speed operation Registers and memory values can be examined and altered The ADSP-2185s flexible architecture and comprehensive PC upload and download functions instruction set allow the processor to perform multiple opera- Instruction-level emulation of program booting and execution tions in parallel. In one processor cycle the ADSP-2185 can: Complete assembly and disassembly of instructions generate the next program address C source-level debugging fetch the next instruction See Designing An EZ-ICE *-Compatible Target System in the perform one or two data moves ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as update one or two data address pointers well as the Target Board Connector for EZ-ICE * Probe sec- perform a computational operation tion of this data sheet for the exact specifications of the EZ-ICE * This takes place while the processor continues to: target board connector. receive and transmit data through the two serial ports Additional Information receive and/or transmit data through the internal DMA port This data sheet provides a general overview of ADSP-2185 receive and/or transmit data through the byte DMA port functionality. For additional information on the architecture and decrement timer instruction set of the processor, refer to the ADSP-2100 Family Development System Users Manual. For more information about the development The ADSP-2100 Family Development Software, a complete set tools, refer to the ADSP-2100 Family Development Tools Data of tools for software and hardware system development, sup- Sheet. ports the ADSP-2185. The System Builder provides a high level method for defining the architecture of systems under develop- ARCHITECTURE OVERVIEW ment. The Assembler has an algebraic syntax that is easy to The ADSP-2185 instruction set provides flexible data moves program and debug. The Linker combines object files into an and multifunction (one or two data moves with a computation) executable file. The Simulator provides an interactive instruction- instructions. Every instruction can be executed in a single pro- level simulation with a reconfigurable user interface to display cessor cycle. The ADSP-2185 assembly language uses an alge- different portions of the hardware environment. A PROM braic syntax for ease of coding and readability. A comprehensive Splitter generates PROM programmer compatible files. The set of development tools supports program development. C Compiler, based on the Free Software Foundations GNU C Compiler, generates ADSP-2185 assembly source code. The POWER-DOWN CONTROL source code debugger allows programs to be corrected in the FULL MEMORY MODE MEMORY C environment. The Runtime Library includes over 100 ANSI- PROGRAMMABLE DATA ADDRESS I/O 16k 3 24 16k 3 16 EXTERNAL GENERATORS PROGRAM standard mathematical and DSP-specific functions. AND ADDRESS SEQUENCER PROGRAM DATA FLAGS DAG 1 DAG 2 MEMORY MEMORY BUS The EZ-KIT Lite is a hardware/software kit offering a complete EXTERNAL DATA PROGRAM MEMORY ADDRESS development environment for the entire ADSP-21xx family: an BUS ADSP-218x based evaluation board with PC monitor software DATA MEMORY ADDRESS BYTE DMA CONTROLLER plus Assembler, Linker, Simulator and PROM Splitter software. PROGRAM MEMORY DATA OR The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hard- DATA MEMORY DATA EXTERNAL ware platform on which you can quickly get started with your DATA BUS DSP software design. The EZ-KIT Lite includes the following ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL features: ALU MAC SHIFTER SPORT 0 SPORT 1 DMA PORT 33 MHz ADSP-2181 ADSP-2100 BASE HOST MODE ARCHITECTURE Full 16-bit Stereo Audio I/O with AD1847 SoundPort * Codec RS-232 Interface to PC with Windows 3.1 Control Software Stand-Alone Operation with Socketed EPROM Figure 1. Block Diagram * EZ-ICE Connector for Emulator Control Figure 1 is an overall block diagram of the ADSP-2185. The DSP Demo Programs processor contains three independent computational units: the The ADSP-218x EZ-ICE * Emulator aids in the hardware ALU, the multiplier/accumulator (MAC) and the shifter. The debugging of an ADSP-2185 system. The emulator consists of computational units process 16-bit data directly and have provi- hardware, host computer resident software, and the target board sions to support multiprecision computations. The ALU per- connector. The ADSP-2185 integrates on-chip emulation sup- forms a standard set of arithmetic and logic operations division port with a 14-pin ICE-PORT* interface. This interface pro- primitives are also supported. The MAC performs single-cycle vides a simpler target board connection that requires fewer multiply, multiply/add and multiply/subtract operations with 40 mechanical clearance considerations than other ADSP-2100 bits of accumulation. The shifter performs logical and arith- Family EZ-ICE *s. The ADSP-2185 device need not be removed metic shifts, normalization, denormalization and derive expo- from the target system when using the EZ-ICE *, nor are any nent operations. adapters needed. Due to the small footprint of the EZ-ICE * The shifter can be used to efficiently implement numeric connector, emulation can be supported in final board designs. format control including multiword and block floating-point *All trademarks are the property of their respective holders. representations. *EZ-ICE and SoundPORT are registered trademarks of Analog Devices, Inc. REV. 0 2