DSP a Microcomputer ADSP-2185M FEATURES System Interface Performance Flexible I/O Structure Allows 2.5 V or 3.3 V Operation 13.3 ns Instruction Cycle Time 2.5 V (Internal), All Inputs Tolerate up to 3.6 V Regardless of Mode 75 MIPS Sustained Performance 16-Bit Internal DMA Port for High-Speed Access to Single-Cycle Instruction Execution On-Chip Memory (Mode Selectable) Single-Cycle Context Switch 4 MByte Memory Interface for Storage of Data Tables 3-Bus Architecture Allows Dual Operand Fetches in and Program Overlays (Mode Selectable) Every Instruction Cycle 8-Bit DMA to Byte Memory for Transparent Program Multifunction Instructions and Data Memory Transfers (Mode Selectable) Power-Down Mode Featuring Low CMOS Standby Power I/O Memory Interface with 2048 Locations Supports Dissipation with 200 CLKIN Cycle Recovery from Parallel Peripherals (Mode Selectable) Power-Down Condition Programmable Memory Strobe and Separate I/O Low Power Dissipation in Idle Mode Memory Space Permits Glueless System Design Programmable Wait State Generation Integration Two Double-Buffered Serial Ports with Companding ADSP-2100 Family Code Compatible (Easy to Use Hardware and Automatic Data Buffering Algebraic Syntax), with Instruction Set Extensions Automatic Booting of On-Chip Program Memory from 80K Bytes of On-Chip RAM, Configured as Byte-Wide External Memory, e.g., EPROM, or 16K Words Program Memory RAM through Internal DMA Port 16K Words Data Memory RAM Six External Interrupts Dual-Purpose Program Memory for Both Instruction and 13 Programmable Flag Pins Provide Flexible System Data Storage Signaling Independent ALU, Multiplier/Accumulator, and Barrel UART Emulation through Software SPORT Reconfiguration Shifter Computational Units ICE-Port Emulator Interface Supports Debugging in Two Independent Data Address Generators Final Systems Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS PROGRAMMABLE EXTERNAL PROGRAM DATA GENERATORS PROGRAM I/O ADDRESS MEMORY MEMORY SEQUENCER AND BUS DAG1 DAG2 16K 24 BIT 16K 16 BIT FLAGS EXTERNAL DATA PROGRAM MEMORY ADDRESS BUS BYTE DMA DATA MEMORY ADDRESS CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS TIMER SPORT0 SPORT1 ALU MAC SHIFTER INTERNAL DMA PORT ADSP-2100 BASE ARCHITECTURE HOST MODE ICE-Port is a trademark of Analog Devices, Inc. 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Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties Tel: 781/329-4700 World Wide Web Site: ADSP-2185M TABLE OF CONTENTS RECOMMENDED OPERATING CONDITIONS . 18 FEATURES 1 ELECTRICAL CHARACTERISTICS . 18 FUNCTIONAL BLOCK DIAGRAM 1 ABSOLUTE MAXIMUM RATINGS . 19 GENERAL DESCRIPTION 3 TIMING SPECIFICATIONS . 19 DEVELOPMENT SYSTEM . 3 GENERAL NOTES . 19 Additional Information 3 TIMING NOTES . 19 ARCHITECTURE OVERVIEW 4 MEMORY TIMING SPECIFICATIONS 19 Serial Ports 5 FREQUENCY DEPENDENCY FOR PIN DESCRIPTIONS 5 TIMING SPECIFICATIONS 20 Common-Mode Pins 6 ENVIRONMENTAL CONDITIONS . 20 Memory Interface Pins . 7 POWER DISSIPATION 20 Full Memory Mode Pins (Mode C = 0) 7 Output Drive Currents 20 Host Mode Pins (Mode C = 1) 7 Capacitive Loading 21 Terminating Unused Pins 8 TEST CONDITIONS . 22 Pin Terminations . 8 Output Disable Time . 22 Interrupts . 9 Output Enable Time . 22 LOW POWER OPERATION . 9 Clock Signals and Reset . 23 Power-Down 9 Interrupts and Flags 24 Idle 9 Bus RequestBus Grant . 25 Slow Idle 10 Memory Read 26 SYSTEM INTERFACE 10 Memory Write 27 Clock Signals . 10 Serial Ports . 28 RESET . 11 IDMA Address Latch . 29 Power Supplies 11 IDMA Write, Short Write Cycle 30 MODES OF OPERATION . 11 IDMA Write, Long Write Cycle . 31 Setting Memory Mode 11 IDMA Read, Long Read Cycle . 32 Passive Configuration . 11 IDMA Read, Short Read Cycle . 33 Active Configuration . 12 IDMA Read, Short Read Cycle in Short Read IACK Configuration . 12 Only Mode . 34 MEMORY ARCHITECTURE . 12 100-LEAD LQFP PIN CONFIGURATION 35 Program Memory 12 LQFP Package Pinout 36 Data Memory . 13 144-Ball Mini-BGA Package Pinout . 37 Memory Mapped Registers (New to the Mini-BGA Package Pinout 38 ADSP-2185M) 13 OUTLINE DIMENSIONS I/O Space (Full Memory Mode) . 13 100-Lead Metric Thin Plastic Quad Flatpack Composite Memory Select (CMS) . 14 (LQFP) (ST-100) . 39 Byte Memory Select (BMS) 14 OUTLINE DIMENSIONS Byte Memory . 14 144-Ball Mini-BGA (CA-144) 40 Byte Memory DMA (BDMA, Full Memory Mode) 14 ORDERING GUIDE 40 Internal Memory DMA Port (IDMA Port Host Memory Mode) 15 Tables Bootstrap Loading (Booting) . 15 Table I. Interrupt Priority and Interrupt IDMA Port Booting 16 Vector Addresses . 9 Bus Request and Bus Grant 16 Table II. Modes of Operation 11 Flag I/O Pins . 16 Table III. PMOVLAY Bits 12 Instruction Set Description 16 Table IV. DMOVLAY Bits 13 DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . 16 Table V. Wait States . 14 Target Board Connector for EZ-ICE Probe 17 Table VI. Data Formats 14 Target Memory Interface 17 PM, DM, BM, IOM, AND CM 17 Target System Interface Signals . 17 2 REV. 0