DSP Microcomputer a ADSP-218xN Series PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES 12.5 ns Instruction cycle time 1.8 V (internal), 80 MIPS sus- Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation tained performance All inputs tolerate up to 3.6 V regardless of mode Single-cycle instruction execution 16-bit internal DMA port for high-speed access to on-chip memory (mode selectable) Single-cycle context switch 4M-byte memory interface for storage of data tables and pro- 3-bus architecture allows dual operand fetches in every gram overlays (mode selectable) instruction cycle 8-bit DMA to byte memory for transparent program and data Multifunction instructions memory transfers (mode selectable) Power-down mode featuring low CMOS standby power dissi- Programmable memory strobe and separate I/O memory pation with 200 CLKIN cycle recovery from power-down space permits glueless system design condition Programmable wait state generation Low power dissipation in idle mode Two double-buffered serial ports with companding hardware INTEGRATION FEATURES and automatic data buffering ADSP-2100 family code compatible (easy to use algebraic Automatic booting of on-chip program memory from byte- syntax), with instruction set extensions wide external memory, for example, EPROM, or through Up to 256K byte of on-chip RAM, configured internal DMA Port Up to 48K words program memory RAM Six external interrupts Up to 56K words data memory RAM 13 programmable flag pins provide flexible system signaling Dual-purpose program memory for both instruction and UART emulation through software SPORT reconfiguration data storage ICE-Port emulator interface supports debugging in final Independent ALU, multiplier/accumulator, and barrel shifter systems computational units Two independent data address generators Powerful program sequencer provides zero overhead loop- ing conditional instruction execution Programmable 16-bit interval timer with prescaler 100-lead LQFP and 144-ball BGA POWER-DOWN CONTROL FULL MEMORY MODE MEMORY PROGRAMMABLE PROGRAM EXTERNAL DATA DATA ADDRESS I/O MEMORY MEMORY ADDRESS GENERATORS PROGRAM AND UP TO UP TO BUS FLAGS DAG1 DAG2 SEQUENCER 48K 24-BIT 56K 16-BIT EXTERNAL DATA BUS PROGRAM MEMORY ADDRESS BYTE DMA DATA MEMORY ADDRESS CONTROLLER PROGRAM MEMORY DATA OR DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL ALU MAC SHIFTER SPORT0 SPORT1 DMA PORT ADSP-2100 BASE ARCHITECTURE HOST MODE Figure 1. Functional Block Diagram ICE-Port is a trademark of Analog Devices, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A. infringements of patents or other rights of third parties that may result from its use. Tel: 781.329.4700 www.analog.com Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Fax: 781.461.3113 2006 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners.ADSP-218xN TABLE OF CONTENTS General Description ................................................. 3 REVISION HISTORY Architecture Overview ........................................... 3 8/06Rev. 0 to Rev. A Modes Of Operation .............................................. 5 Miscellaneous Format Updates.......................... Universal Interrupts ........................................................... 5 Applied Corrections or Additional Information to: Low-power Operation ............................................ 6 Clock Signals ....................................................... 8 System Interface ................................................... 7 External Crystal Connections .................................. 8 Reset .................................................................. 8 ADSP-2185 Memory Architecture ............................ 9 Power Supplies ..................................................... 8 Electrical Characteristics ....................................... 22 Memory Architecture ............................................ 9 Absolute Maximum Ratings ................................... 23 Bus Request and Bus Grant ................................... 14 ESD Diode Protection .......................................... 24 Flag I/O Pins ..................................................... 15 Memory Read ..................................................... 31 Instruction Set Description ................................... 15 Memory Write .................................................... 32 Development System ........................................... 15 Serial Ports ........................................................ 33 Additional Information ........................................ 17 Outline Dimensions ............................................. 45 Pin Descriptions .................................................... 18 Ordering Guide .................................................. 47 Memory Interface Pins ......................................... 19 Terminating Unused Pins ..................................... 19 Specifications ........................................................ 22 Recommended Operating Conditions ...................... 22 Electrical Characteristics ....................................... 22 Absolute Maximum Ratings .................................. 23 ESD Sensitivity ................................................... 23 ESD Diode Protection .......................................... 24 Power Dissipation ............................................... 24 Environmental Conditions .................................... 25 Test Conditions .................................................. 25 Timing Specifications .......................................... 26 LQFP Package Pinout .......................................... 40 BGA Package Pinout ........................................... 42 Outline Dimensions ............................................... 45 Surface Mount Design .......................................... 46 Ordering Guide ..................................................... 47 Rev. A Page 2 of 48 August 2006