a DSP Microcomputer ADSP-2189M FEATURES FUNCTIONAL BLOCK DIAGRAM PERFORMANCE POWER-DOWN CONTROL 13.3 ns Instruction Cycle Time 2.5 Volts (Internal), FULL MEMORY 75 MIPS Sustained Performance MEMORY MODE PROGRAMMABLE DATA ADDRESS PROGRAM DATA I/O Single-Cycle Instruction Execution PROGRAM EXTERNAL GENERATORS MEMORY MEMORY AND SEQUENCER ADDRESS 32K 48K FLAGS DAG 2 BUS Single-Cycle Context Switch DAG 1 24 BIT 16 BIT 3-Bus Architecture Allows Dual Operand Fetches in EXTERNAL DATA PROGRAM MEMORY ADDRESS BUS Every Instruction Cycle DATA MEMORY ADDRESS Multifunction Instructions BYTE DMA CONTROLLER PROGRAM MEMORY DATA Power-Down Mode Featuring Low CMOS Standby OR Power Dissipation with 200 CLKIN Cycle Recovery DATA MEMORY DATA EXTERNAL from Power-Down Condition DATA BUS Low Power Dissipation in Idle Mode ARITHMETIC UNITS SERIAL PORTS TIMER INTERNAL ALU SHIFTER SPORT 0 SPORT 1 MAC DMA PORT INTEGRATION ADSP-2100 BASE HOST MODE ADSP-2100 Family Code Compatible (Easy to Use Alge- ARCHITECTURE braic Syntax), with Instruction Set Extensions 192K Bytes of On-Chip RAM, Configured as 32K Words Six External Interrupts On-Chip Program Memory RAM and 48K Words On- 13 Programmable Flag Pins Provide Flexible System Chip Data Memory RAM Signaling Dual Purpose Program Memory for Both Instruction UART Emulation through Software SPORT Reconfiguration and Data Storage ICE-Port Emulator Interface Supports Debugging in Independent ALU, Multiplier/Accumulator and Barrel Final Systems Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution GENERAL DESCRIPTION Programmable 16-Bit Interval Timer with Prescaler The ADSP-2189M is a single-chip microcomputer optimized 100-Lead LQFP for digital signal processing (DSP) and other high speed nu- meric processing applications. SYSTEM INTERFACE Flexible I/O Structure Allows 2.5 V or 3.3 V Operation The ADSP-2189M combines the ADSP-2100 family base archi- All Inputs Tolerate Up to 3.6 V, Regardless of Mode tecture (three computational units, data address generators and 16-Bit Internal DMA Port for High Speed Access to On- a program sequencer) with two serial ports, a 16-bit internal Chip Memory (Mode Selectable) DMA port, a byte DMA port, a programmable timer, Flag I/O, 4 MByte Memory Interface for Storage of Data Tables extensive interrupt capabilities, and on-chip program and data and Program Overlays (Mode Selectable) memory. 8-Bit DMA to Byte Memory for Transparent Program The ADSP-2189M integrates 192K bytes of on-chip memory and Data Memory Transfers (Mode Selectable) configured as 32K words (24-bit) of program RAM and 48K I/O Memory Interface with 2048 Locations Supports words (16-bit) of data RAM. Power-down circuitry is also pro- Parallel Peripherals (Mode Selectable) vided to meet the low power needs of battery operated portable Programmable Memory Strobe and Separate I/O equipment. The ADSP-2189M is available in a 100-lead LQFP Memory Space Permits Glueless System Design package. Programmable Wait-State Generation In addition, the ADSP-2189M supports new instructions, which Two Double-Buffered Serial Ports with Companding include bit manipulationsbit set, bit clear, bit toggle, bit test Hardware and Automatic Data Buffering new ALU constants, new multiplication instruction (x squared), Automatic Booting of On-Chip Program Memory from biased rounding, result free ALU operations, I/O memory trans- Byte-Wide External Memory, e.g., EPROM, or fers and global interrupt masking, for increased flexibility. Through Internal DMA Port ICE-Port is a trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: ADSP-2189M The EZ-ICE performs a full range of functions, including: Fabricated in a high speed, low power, CMOS process, the ADSP-2189M operates with a 13.3 ns instruction cycle time. In-target operation Every instruction can execute in a single processor cycle. Up to 20 breakpoints Single-step or full-speed operation The ADSP-2189Ms flexible architecture and comprehensive Registers and memory values can be examined and altered instruction set allow the processor to perform multiple opera- PC upload and download functions tions in parallel. In one processor cycle, the ADSP-2189M can: Instruction-level emulation of program booting and execution Generate the next program address Complete assembly and disassembly of instructions Fetch the next instruction C source-level debugging Perform one or two data moves See Designing An EZ-ICE-Compatible Target System in the Update one or two data address pointers ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as Perform a computational operation well as the Designing an EZ-ICE compatible System section of This takes place while the processor continues to: this data sheet for the exact specifications of the EZ-ICE target Receive and transmit data through the two serial ports board connector. Receive and/or transmit data through the internal DMA port Additional Information Receive and/or transmit data through the byte DMA port This data sheet provides a general overview of ADSP-2189M Decrement timer functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-2100 Family DEVELOPMENT SYSTEM Users Manual, Third Edition. For more information about the The ADSP-2100 Family Development Software, a complete set development tools, refer to the ADSP-2100 Family Develop- of tools for software and hardware system development, sup- ment Tools Data Sheet. ports the ADSP-2189M. The System Builder provides a high level method for defining the architecture of systems under ARCHITECTURE OVERVIEW development. The Assembler has an algebraic syntax that is easy The ADSP-2189M instruction set provides flexible data moves to program and debug. The Linker combines object files into an and multifunction (one or two data moves with a computation) executable file. The Simulator provides an interactive instruc- instructions. Every instruction can be executed in a single pro- tion-level simulation with a reconfigurable user interface to cessor cycle. The ADSP-2189M assembly language uses an display different portions of the hardware environment. algebraic syntax for ease of coding and readability. A compre- A PROM Splitter generates PROM programmer compatible hensive set of development tools supports program development. files. The C Compiler, based on the Free Software Foundations POWER-DOWN GNU C Compiler, generates ADSP-2189M assembly source CONTROL FULL MEMORY code. The source code debugger allows programs to be cor- MEMORY MODE PROGRAMMABLE DATA ADDRESS PROGRAM DATA rected in the C environment. The Runtime Library includes over I/O PROGRAM GENERATORS EXTERNAL MEMORY MEMORY AND SEQUENCER ADDRESS 32K 48K 100 ANSI-standard mathematical and DSP-specific functions. FLAGS DAG 2 DAG 1 BUS 24 BIT 16 BIT EXTERNAL The EZ-KIT Lite is a hardware/software kit offering a complete DATA PROGRAM MEMORY ADDRESS BUS development environment for the entire ADSP-21xx family: an DATA MEMORY ADDRESS BYTE DMA ADSP-218x-based evaluation board with PC monitor software CONTROLLER PROGRAM MEMORY DATA plus Assembler, Linker, Simulator and PROM Splitter software. OR DATA MEMORY DATA The ADSP-218x EZ-KIT Lite is a low cost, easy to use hard- EXTERNAL DATA ware platform on which you can quickly get started with your BUS ARITHMETIC UNITS SERIAL PORTS TIMER DSP software design. The EZ-KIT Lite includes the following INTERNAL ALU MAC SHIFTER SPORT 0 SPORT 1 DMA features: PORT ADSP-2100 BASE HOST MODE 33 MHz ADSP-218x ARCHITECTURE Full 16-bit Stereo Audio I/O with AD1847 SoundPort Figure 1. Functional Block Diagram Codec RS-232 Interface to PC with Windows 3.1 Control Software Figure 1 is an overall block diagram of the ADSP-2189M. The EZ-ICE Connector for Emulator Control processor contains three independent computational units: the DSP Demo Programs ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- The ADSP-218x EZ-ICE Emulator aids in the hardware de- sions to support multiprecision computations. The ALU per- bugging of an ADSP-2189M system. The emulator consists of forms a standard set of arithmetic and logic operations division hardware, host computer resident software and the target board primitives are also supported. The MAC performs single-cycle connector. The ADSP-2189M integrates on-chip emulation multiply, multiply/add and multiply/subtract operations with 40 support with a 14-pin ICE-Port interface. This interface pro- bits of accumulation. The shifter performs logical and arith- vides a simpler target board connection that requires fewer metic shifts, normalization, denormalization and derive expo- mechanical clearance considerations than other ADSP-2100 nent operations. Family EZ-ICEs. The ADSP-2189M device need not be re- moved from the target system when using the EZ-ICE, nor are The shifter can be used to efficiently implement numeric any adapters needed. Due to the small footprint of the EZ-ICE format control including multiword and block floating-point connector, emulation can be supported in final board designs. representations. EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc. 2 REV. A