a DSP Microcomputer Preliminary Technical Data ADSP-2195 ADSP-219x DSP CORE FEATURES Independent ALU, Multiplier/Accumulator, and Barrel 6.25 ns Instruction Cycle Time (Internal), for up to Shifter Computational Units with Dual 40-bit 160 MIPS Sustained Performance Accumulators ADSP-218x Family Code Compatible with the Same Single-Cycle Context Switch between Two Sets of Easy -to-Use Algebraic Syntax Computational and DAG Registers Single-Cycle Instruction Execution Parallel Execution of Computation and Memory Up to 16M words of Addressable Memory Space with Instructions 24 Bits of Addressing Width Pipelined Architecture Supports Efficient Code Dual Purpose Program Memory for Both Instruction and Execution at Speeds up to 160 MIPS Data Storage Register File Computations with All Nonconditional, Fully Transparent Instruction Cache Allows Dual Nonparallel Computational Instructions Operand Fetches in Every Instruction Cycle Powerful Program Sequencer Provides Zero-Overhead Unified Memory Space Permits Flexible Address Looping and Conditional Instruction Execution Generation, Using Two Independent DAG Units Architectural Enhancements for Compiled C Code Efficiency FUNCTIONAL BLOCK DIAGRAM % & REV. PrA This information applies to a product under development. Its characteristics One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. and specifications are subject to change without notice. Analog Devices Tel:781/329-4700 World Wide Web Site: For current information contact Analog Devices at 800/262-5643 ADSP-2195 September 2001 ADSP-2195 DSP FEATURES External Memory Interface Features Include: 32K Words of On-Chip RAM, Configured as 16K Words Direct Access from the DSP to External Memory for On-Chip 24-bit RAM and 16K Words On-Chip Data and Instructions. 16-bit RAM Support for DMA Block Transfers to/from 16K Words of On-Chip 24-bit ROM External Memory. Architecture Enhancements beyond ADSP-218x Family Separate Peripheral Memory Space with Parallel are Supported with Instruction Set Extensions for Support for 224K External 16-Bit Registers. Added Registers, Ports, and Peripherals Four General-Purpose Memory Select Signals that Flexible Power Management with Selectable Provide Access to Separate Banks of External Power-Down and Idle Modes Memory. Bank Boundaries and Size Are User- Programmable PLL Supports 1 to 32 Frequency Programmable. Multiplication, Enabling Full-Speed Operation from Programmable Waitstate Logic with ACK Signal and Low-Speed Input Clocks Separate Read and Write Wait Counts. Wait Mode 2.5 V Internal Operation Supports 3.3 V Compliant I/O Completion Supports All Combinations of ACK Three Full-Duplex Multichannel Serial Ports, Each and/or Wait Count. Supporting H.100 Standard with A-Law and -Law I/O Clock Rate Can Be Set to the Peripheral Clock Rate Companding in Hardware Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow Two SPI-Compatible Ports with DMA Capability Memory Devices. One UART Port with DMA Capability Address Translation and Data Word Packing is Provided 16 General-Purpose I/O Pins (Eight Dedicated/Eight to Support an 8- or 16-Bit External Data Bus. Programmable from the External Memory Interface) Programmable Read and Write Strobe Polarity. with Integrated Interrupt Support Separate Configuration Registers for the Four Three Programmable 32-Bit Interval Timers with General-Purpose, Peripheral, and Boot Pulsewidth Counter, PWM Generation, and Externally Memory Spaces. Clocked Timer Capabilities Bus Request and Grant Signals Support the Use of the Up to 11 DMA Channels can be Active at any Given Time External Bus by an External Device. Host Port With DMA Capability for Efficient, Glueless Host Boot Methods Include Booting Through External Memory Interface (16-Bit Transfers) Interface, SPI Ports, UART Port, or Host Interface IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 144-Lead LQFP Package (20 20 1.4 mm) and 144-Lead Mini-BGA Package (10 10 1.25 mm) This information applies to a product under development. Its characteristics and specifications are subject to change with- 2 REV. PrA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.