a DSP Microcomputer Preliminary Technical Data ADSP-2196 ADSP-219x DSP CORE FEATURES Independent ALU, Multiplier/Accumulator, and Barrel 6.25 ns Instruction Cycle Time (Internal), for up to Shifter Computational Units with Dual 40-bit 160 MIPS Sustained Performance Accumulators ADSP-218x Family Code Compatible with the Same Single-Cycle Context Switch between Two Sets of Easy -to-Use Algebraic Syntax Computational and DAG Registers Single-Cycle Instruction Execution Parallel Execution of Computation and Memory Up to 16M words of Addressable Memory Space with Instructions 24 Bits of Addressing Width Pipelined Architecture Supports Efficient Code Dual Purpose Program Memory for Both Instruction and Execution at Speeds up to 160 MIPS Data Storage Register File Computations with All Nonconditional, Fully Transparent Instruction Cache Allows Dual Nonparallel Computational Instructions Operand Fetches in Every Instruction Cycle Powerful Program Sequencer Provides Zero-Overhead Unified Memory Space Permits Flexible Address Looping and Conditional Instruction Execution Generation, Using Two Independent DAG Units Architectural Enhancements for Compiled C Code Efficiency FUNCTIONAL BLOCK DIAGRAM % & REV. PrA This information applies to a product under development. Its characteristics One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. and specifications are subject to change without notice. Analog Devices Tel:781/329-4700 World Wide Web Site: For current information contact Analog Devices at 800/262-5643 ADSP-2196 September 2001 ADSP-2196 DSP FEATURES External Memory Interface Features Include: 16K Words of On-Chip RAM, Configured as 8K Words Direct Access from the DSP to External Memory for On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM Data and Instructions. 16K Words of On-Chip 24-bit ROM Support for DMA Block Transfers to/from Architecture Enhancements beyond ADSP-218x Family External Memory. are Supported with Instruction Set Extensions for Separate Peripheral Memory Space with Parallel Added Registers, Ports, and Peripherals Support for 224K External 16-Bit Registers. Flexible Power Management with Selectable Four General-Purpose Memory Select Signals that Power-Down and Idle Modes Provide Access to Separate Banks of External Programmable PLL Supports 1 to 32 Frequency Memory. Bank Boundaries and Size Are User- Multiplication, Enabling Full-Speed Operation from Programmable. Low-Speed Input Clocks Programmable Waitstate Logic with ACK Signal and 2.5 V Internal Operation Supports 3.3 V Compliant I/O Separate Read and Write Wait Counts. Wait Mode Three Full-Duplex Multichannel Serial Ports, Each Completion Supports All Combinations of ACK Supporting H.100 Standard with A-Law and -Law and/or Wait Count. Companding in Hardware I/O Clock Rate Can Be Set to the Peripheral Clock Rate Two SPI-Compatible Ports with DMA Capability Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow One UART Port with DMA Capability Memory Devices. 16 General-Purpose I/O Pins (Eight Dedicated/Eight Address Translation and Data Word Packing is Provided Programmable from the External Memory Interface) to Support an 8- or 16-Bit External Data Bus. with Integrated Interrupt Support Programmable Read and Write Strobe Polarity. Three Programmable 32-Bit Interval Timers with Separate Configuration Registers for the Four Pulsewidth Counter, PWM Generation, and Externally General-Purpose, Peripheral, and Boot Clocked Timer Capabilities Memory Spaces. Up to 11 DMA Channels can be Active at any Given Time Bus Request and Grant Signals Support the Use of the Host Port With DMA Capability for Efficient, Glueless Host External Bus by an External Device. Interface (16-Bit Transfers) Boot Methods Include Booting Through External Memory Interface, SPI Ports, UART Port, or Host Interface IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 144-Lead LQFP Package (20 20 1.4 mm) and 144-Lead Mini-BGA Package (10 10 1.25 mm) This information applies to a product under development. Its characteristics and specifications are subject to change with- 2 REV. PrA out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.