Blackfin Embedded Processor ADSP-BF504/ADSP-BF504F/ADSP-BF506F FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor Two 32-bit up/down counters with rotary support Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, Eight 32-bit timers/counters with PWM support 40-bit shifter Two 3-phase 16-bit center-based PWM units RISC-like register and instruction model for ease of 2 dual-channel, full-duplex synchronous serial ports 2 programming and compiler-friendly support (SPORTs), supporting eight stereo I S channels Advanced debug, trace, and performance monitoring 2 serial peripheral interface (SPI) compatible ports Accepts a range of supply voltages for internal and I/O opera- 2 UARTs with IrDA support tions. See Operating Conditions on Page 26 Parallel peripheral interface (PPI), supporting ITU-R 656 Internal 32M bit flash (available on ADSP-BF504F and video data formats ADSP-BF506F processors) Removable storage interface (RSI) controller for MMC, SD, Internal ADC (available on ADSP-BF506F processor) SDIO, and CE-ATA Off-chip voltage regulator interface Internal ADC with 12 channels, 12 bits, and up to 2 MSPS 88-lead (12 mm 12 mm) LFCSP package for ADSP-BF504 ADC controller module (ACM), providing a glueless interface and ADSP-BF504F processors between Blackfin processor and internal or external ADC 120-lead (14 mm 14 mm) LQFP package for ADSP-BF506F Controller Area Network (CAN) controller processor 2-wire interface (TWI) controller 12 peripheral DMAs MEMORY 2 memory-to-memory DMA channels 68K bytes of L1 SRAM (processor core-accessible) memory Event handler with 52 interrupt inputs (See Table 1 on Page 3 for L1 and L3 memory size details) 35 general-purpose I/Os (GPIOs), with programmable External (interface-accessible) memory controller with glue- hysteresis less support for internal 32M bit flash and boot ROM Debug/JTAG interface Flexible booting options from internal flash and SPI memory On-chip PLL capable of frequency multiplication or from host devices including SPI, PPI, and UART Memory management unit providing memory protection COUNTER10 WATCHDOG TIMER GPIO TIMER70 VOLTAGE REGULATOR INTERFACE JTAG TEST AND EMULATION PWM 10 PERIPHERAL PORT F ACCESS BUS SPORT10 PORT G INTERRUPT SPI10 CONTROLLER B UART10 PORT H L1 INSTRUCTION L1 DATA PPI DMA MEMORY MEMORY CONTROLLER DMA RSI EAB 16 ACCESS BUS DCB ACM ADC DEB CAN BOOT 32M BIT MEMORY PORT TWI FLASH FLASH CONTROL ROM Figure 1. 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Technical Support www.analog.comADSP-BF504/ADSP-BF504F/ADSP-BF506F TABLE OF CONTENTS Features ................................................................. 1 Additional Information ........................................ 21 Memory ................................................................ 1 Related Signal Chains ........................................... 21 Peripherals ............................................................. 1 Signal Descriptions ................................................. 22 General Description ................................................. 3 Specifications ........................................................ 26 Portable Low-Power Architecture ............................. 3 Operating Conditions ........................................... 26 System Integration ................................................ 3 Electrical Characteristics ....................................... 28 Processor Peripherals ............................................. 3 ProcessorAbsolute Maximum Ratings ................... 31 Blackfin Processor Core .......................................... 4 ESD Sensitivity ................................................... 32 Memory Architecture ............................................ 5 Package Information ............................................ 32 Flash Memory ...................................................... 9 ProcessorTiming Specifications ........................... 33 DMA Controllers .................................................. 9 ProcessorOutput Drive Currents .......................... 50 Watchdog Timer .................................................. 9 ProcessorTest Conditions ................................... 51 Timers ............................................................... 9 ProcessorEnvironmental Conditions ..................... 53 Up/Down Counters and Thumbwheel Interfaces ........ 10 FlashSpecifications .............................................. 54 3-Phase PWM Units ............................................ 10 FlashProgram and Erase Times and Endurance Cycles ............................................................ 54 Serial Ports ........................................................ 10 FlashAbsolute Maximum Ratings ......................... 54 Serial Peripheral Interface (SPI) Ports ...................... 11 ADCSpecifications ............................................... 55 UART Ports (UARTs) .......................................... 11 ADCOperating Conditions ................................. 55 Parallel Peripheral Interface (PPI) ........................... 11 ADCTiming Specifications ................................. 58 RSI Interface ...................................................... 12 ADCAbsolute Maximum Ratings ......................... 58 Controller Area Network (CAN) Interface ................ 12 ADCTypical Performance Characteristics .............. 59 TWI Controller Interface ...................................... 13 ADCTerminology ............................................ 61 Ports ................................................................ 13 ADCTheory of Operation ................................... 62 Dynamic Power Management ................................ 13 ADCModes of Operation ................................... 68 ADSP-BF50x Voltage Regulation ............................ 15 ADCSerial Interface .......................................... 71 Clock Signals ..................................................... 15 120-Lead LQFP Lead Assignment ............................... 73 Booting Modes ................................................... 16 88-Lead LFCSP Lead Assignment ............................... 76 Instruction Set Description ................................... 17 Outline Dimensions ................................................ 79 Development Tools ............................................. 17 Automotive Products .............................................. 81 ADC and ACM Interface ...................................... 18 Ordering Guide ..................................................... 81 Internal ADC ..................................................... 20 ADC Application Hints ........................................ 21 REVISION HISTORY 04/14Rev. A to Rev. B Revised package diagram (Figure 93) to include U-Groove in Outline Dimensions ................................................ 79 Updated Development Tools .................................... 17 Package thickness changed from 0.75/0.80/0.85 to Corrected RCKFE bit setting and description in 0.75/0.85/0.90 in Figure 94 in Outline Dimensions ......... 79 Table 9, The SPORTx Receive Configuration 1 Register (SPORTx RCR1) ................................................... 19 Updated footnote 6 in Operating Conditions ................ 26 Updated Table 18 with revised data for Static CurrentIDD-DEEPSLEEP (mA) ..................... 30 Rev. B Page 2 of 84 April 2014