Blackfin Embedded Processor ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F FEATURES PERIPHERALS Up to 400 MHz high performance Blackfin processor IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588 support (ADSP-BF518/ADSP-BF518F only) Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats RISC-like register and instruction model for ease of programming and compiler-friendly support 2 dual-channel, full-duplex synchronous serial ports 2 (SPORTs), supporting 8 stereo I S channels Advanced debug, trace, and performance monitoring 12 peripheral DMAs, 2 mastered by the Ethernet MAC Wide range of operating voltages. See Operating Conditions on Page 20 2 memory-to-memory DMAs with external request lines Qualified for Automotive Applications. See Automotive Event handler with 56 interrupt inputs Products on Page 65 2 serial peripheral interfaces (SPI) 168-ball CSP BGA or 176-lead LQFP with exposed pad Removable storage interface (RSI) controller for MMC, SD, SDIO, and CE-ATA MEMORY 2 UARTs with IrDA support 116K bytes of on-chip memory 2-wire interface (TWI) controller External memory controller with glueless support for SDRAM Eight 32-bit timers/counters with PWM support and asynchronous 8-bit and 16-bit memories 3-phase 16-bit center-based PWM unit Optional 4M bit SPI flash with boot option 32-bit general-purpose counter Flexible booting options from internal SPI flash, OTP Real-time clock (RTC) and watchdog timer memory, external SPI/parallel memories, or from SPI/UART 32-bit core timer host devices 40 general-purpose I/Os (GPIOs) Code security with Lockbox secure technology Debug/JTAG interface One-time-programmable (OTP) memory On-chip PLL capable of frequency multiplication Memory management unit providing memory protection RTC OTP WATCHDOG TIMER PERIPHERAL ACCESS BUS COUNTER JTAG TEST AND EMULATION 3-PHASE PWM TIMER70 TWI INTERRUPT CONTROLLER B SPORT1-0 PORTS RSI (SDIO) L1 L1 DMA INSTRUCTION PPI DATA CONTROLLER MEMORY MEMORY UART10 DMA EXTERNAL EMAC 16 DMA CORE BUS BUS EXTERNAL ACCESS BUS SPI1 EXTERNAL PORT BOOT SPI0 ROM FLASH, SDRAM CONTROL 4 Mbit SPI Flash (See Table 1) Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 2011 Analog Devices, Inc. All rights reserved.ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F TABLE OF CONTENTS Features ................................................................. 1 Related Signal Chains ........................................... 16 Memory ................................................................ 1 Lockbox Secure Technology Disclaimer .................... 16 Peripherals ............................................................. 1 Signal Descriptions ................................................. 17 Revision History ...................................................... 2 Specifications ........................................................ 20 General Description ................................................. 3 Operating Conditions ........................................... 20 Portable Low Power Architecture ............................. 3 Electrical Characteristics ....................................... 22 System Integration ................................................ 3 Flash Memory Characteristics ................................ 24 Blackfin Processor Core .......................................... 3 Absolute Maximum Ratings ................................... 25 Memory Architecture ............................................ 5 Package Information ............................................ 26 Event Handling .................................................... 6 ESD Sensitivity ................................................... 26 DMA Controllers .................................................. 7 Timing Specifications ........................................... 27 Processor Peripherals ............................................. 7 Output Drive Currents ......................................... 50 Dynamic Power Management ................................ 11 Test Conditions .................................................. 52 Voltage Regulation Interface .................................. 13 Thermal Characteristics ........................................ 56 Clock Signals ..................................................... 13 176-Lead LQFP Lead Assignment ............................... 57 Booting Modes ................................................... 14 168-Ball CSP BGA Ball Assignment ........................... 60 Instruction Set Description ................................... 15 Outline Dimensions ................................................ 63 Development Tools ............................................. 15 Surface-Mount Design .......................................... 64 Designing an Emulator-Compatible Automotive Products .............................................. 65 Processor Board (Target) ................................... 16 Ordering Guide ..................................................... 65 Related Documents ............................................. 16 REVISION HISTORY 1/11Rev. A to Rev. B Revised t , t and t specification in RSI Controller Timing WL WH OH (High Speed Mode) ................................................. 36 This data sheet release coincides with the release of the revised ADSP-BF51x Blackfin Processor Hardware Reference. All Revised t and t specifications in 10/100 Ethernet MDCIH MDCOH redundant information has been removed. MAC Controller Timing: MII Station Management ........ 48 Revised several specifications in Operating Conditions ... 20 Corrected dimensions in 168-Ball Chip Scale Package Ball Grid Array CSP BGA (BC-168-1) ................................... 64 Revised f specification in Phase-Locked Loop Operating VCO Conditions ........................................................... 21 Revised several specifications in Electrical Characteristics 22 Added additional f specification for automotive models in CKIN Clock and Reset Timing .......................................... 27 Changed the parameter V to V in Asynchronous DDMEM DDEXT Memory Read Cycle Timing ..................................... 29 SDRAM Interface Timing ........................................ 31 Parallel Peripheral Interface Timing ........................... 33 Serial Ports ........................................................... 37 Revised t specification in Parallel Peripheral Interface Tim- HFSPE ing ..................................................................... 33 Revised t specification and added the t specification in HFSPE PSUD Parallel Peripheral Interface Timing ........................... 33 Revised the t and t specifications in WL WH RSI Controller Timing ............................................ 35 Rev. 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